MOESI_CMP_token.py revision 8931
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34 35# 36# Note: the L1 Cache latency is only used by the sequencer on fast path hits 37# 38class L1Cache(RubyCache): 39 latency = 2 40 41# 42# Note: the L2 Cache latency is not currently used 43# 44class L2Cache(RubyCache): 45 latency = 10 46 47def define_options(parser): 48 parser.add_option("--l1-retries", type="int", default=1, 49 help="Token_CMP: # of l1 retries before going persistent") 50 parser.add_option("--timeout-latency", type="int", default=300, 51 help="Token_CMP: cycles until issuing again"); 52 parser.add_option("--disable-dyn-timeouts", action="store_true", 53 help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 54 parser.add_option("--allow-atomic-migration", action="store_true", 55 help="allow migratory sharing for atomic only accessed blocks") 56 57def create_system(options, system, piobus, dma_ports, ruby_system): 58 59 if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 60 panic("This script requires the MOESI_CMP_token protocol to be built.") 61 62 # 63 # number of tokens that the owner passes to requests so that shared blocks can 64 # respond to read requests 65 # 66 n_tokens = options.num_cpus + 1 67 68 cpu_sequencers = [] 69 70 # 71 # The ruby network creation expects the list of nodes in the system to be 72 # consistent with the NetDest list. Therefore the l1 controller nodes must be 73 # listed before the directory nodes and directory nodes before dma nodes, etc. 74 # 75 l1_cntrl_nodes = [] 76 l2_cntrl_nodes = [] 77 dir_cntrl_nodes = [] 78 dma_cntrl_nodes = [] 79 80 # 81 # Must create the individual controllers before the network to ensure the 82 # controller constructors are called before the network constructor 83 # 84 l2_bits = int(math.log(options.num_l2caches, 2)) 85 block_size_bits = int(math.log(options.cacheline_size, 2)) 86 87 cntrl_count = 0 88 89 for i in xrange(options.num_cpus): 90 # 91 # First create the Ruby objects associated with this cpu 92 # 93 l1i_cache = L1Cache(size = options.l1i_size, 94 assoc = options.l1i_assoc, 95 start_index_bit = block_size_bits) 96 l1d_cache = L1Cache(size = options.l1d_size, 97 assoc = options.l1d_assoc, 98 start_index_bit = block_size_bits) 99 100 l1_cntrl = L1Cache_Controller(version = i, 101 cntrl_id = cntrl_count, 102 L1IcacheMemory = l1i_cache, 103 L1DcacheMemory = l1d_cache, 104 l2_select_num_bits = l2_bits, 105 N_tokens = n_tokens, 106 retry_threshold = \ 107 options.l1_retries, 108 fixed_timeout_latency = \ 109 options.timeout_latency, 110 dynamic_timeout_enabled = \ 111 not options.disable_dyn_timeouts, 112 no_mig_atomic = not \ 113 options.allow_atomic_migration, 114 send_evictions = ( 115 options.cpu_type == "detailed"), 116 ruby_system = ruby_system) 117 118 cpu_seq = RubySequencer(version = i, 119 icache = l1i_cache, 120 dcache = l1d_cache, 121 ruby_system = ruby_system) 122 123 l1_cntrl.sequencer = cpu_seq 124 125 if piobus != None: 126 cpu_seq.pio_port = piobus.slave 127 128 exec("system.l1_cntrl%d = l1_cntrl" % i) 129 # 130 # Add controllers and sequencers to the appropriate lists 131 # 132 cpu_sequencers.append(cpu_seq) 133 l1_cntrl_nodes.append(l1_cntrl) 134 135 cntrl_count += 1 136 137 l2_index_start = block_size_bits + l2_bits 138 139 for i in xrange(options.num_l2caches): 140 # 141 # First create the Ruby objects associated with this cpu 142 # 143 l2_cache = L2Cache(size = options.l2_size, 144 assoc = options.l2_assoc, 145 start_index_bit = l2_index_start) 146 147 l2_cntrl = L2Cache_Controller(version = i, 148 cntrl_id = cntrl_count, 149 L2cacheMemory = l2_cache, 150 N_tokens = n_tokens, 151 ruby_system = ruby_system) 152 153 exec("system.l2_cntrl%d = l2_cntrl" % i) 154 l2_cntrl_nodes.append(l2_cntrl) 155 156 cntrl_count += 1 157 158 phys_mem_size = 0 159 for mem in system.memories.unproxy(system): 160 phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1 161 mem_module_size = phys_mem_size / options.num_dirs 162 163 for i in xrange(options.num_dirs): 164 # 165 # Create the Ruby objects associated with the directory controller 166 # 167 168 mem_cntrl = RubyMemoryControl(version = i) 169 170 dir_size = MemorySize('0B') 171 dir_size.value = mem_module_size 172 173 dir_cntrl = Directory_Controller(version = i, 174 cntrl_id = cntrl_count, 175 directory = \ 176 RubyDirectoryMemory(version = i, 177 size = dir_size), 178 memBuffer = mem_cntrl, 179 l2_select_num_bits = l2_bits, 180 ruby_system = ruby_system) 181 182 exec("system.dir_cntrl%d = dir_cntrl" % i) 183 dir_cntrl_nodes.append(dir_cntrl) 184 185 cntrl_count += 1 186 187 for i, dma_port in enumerate(dma_ports): 188 # 189 # Create the Ruby objects associated with the dma controller 190 # 191 dma_seq = DMASequencer(version = i, 192 ruby_system = ruby_system) 193 194 dma_cntrl = DMA_Controller(version = i, 195 cntrl_id = cntrl_count, 196 dma_sequencer = dma_seq, 197 ruby_system = ruby_system) 198 199 exec("system.dma_cntrl%d = dma_cntrl" % i) 200 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 201 dma_cntrl_nodes.append(dma_cntrl) 202 cntrl_count += 1 203 204 all_cntrls = l1_cntrl_nodes + \ 205 l2_cntrl_nodes + \ 206 dir_cntrl_nodes + \ 207 dma_cntrl_nodes 208 209 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 210