MOESI_CMP_token.py revision 10524
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35 36# 37# Note: the L1 Cache latency is only used by the sequencer on fast path hits 38# 39class L1Cache(RubyCache): 40 latency = 2 41 42# 43# Note: the L2 Cache latency is not currently used 44# 45class L2Cache(RubyCache): 46 latency = 10 47 48def define_options(parser): 49 parser.add_option("--l1-retries", type="int", default=1, 50 help="Token_CMP: # of l1 retries before going persistent") 51 parser.add_option("--timeout-latency", type="int", default=300, 52 help="Token_CMP: cycles until issuing again"); 53 parser.add_option("--disable-dyn-timeouts", action="store_true", 54 help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 55 parser.add_option("--allow-atomic-migration", action="store_true", 56 help="allow migratory sharing for atomic only accessed blocks") 57 58def create_system(options, full_system, system, dma_ports, ruby_system): 59 60 if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 61 panic("This script requires the MOESI_CMP_token protocol to be built.") 62 63 # 64 # number of tokens that the owner passes to requests so that shared blocks can 65 # respond to read requests 66 # 67 n_tokens = options.num_cpus + 1 68 69 cpu_sequencers = [] 70 71 # 72 # The ruby network creation expects the list of nodes in the system to be 73 # consistent with the NetDest list. Therefore the l1 controller nodes must be 74 # listed before the directory nodes and directory nodes before dma nodes, etc. 75 # 76 l1_cntrl_nodes = [] 77 l2_cntrl_nodes = [] 78 dir_cntrl_nodes = [] 79 dma_cntrl_nodes = [] 80 81 # 82 # Must create the individual controllers before the network to ensure the 83 # controller constructors are called before the network constructor 84 # 85 l2_bits = int(math.log(options.num_l2caches, 2)) 86 block_size_bits = int(math.log(options.cacheline_size, 2)) 87 88 for i in xrange(options.num_cpus): 89 # 90 # First create the Ruby objects associated with this cpu 91 # 92 l1i_cache = L1Cache(size = options.l1i_size, 93 assoc = options.l1i_assoc, 94 start_index_bit = block_size_bits) 95 l1d_cache = L1Cache(size = options.l1d_size, 96 assoc = options.l1d_assoc, 97 start_index_bit = block_size_bits) 98 99 l1_cntrl = L1Cache_Controller(version = i, 100 L1Icache = l1i_cache, 101 L1Dcache = l1d_cache, 102 l2_select_num_bits = l2_bits, 103 N_tokens = n_tokens, 104 retry_threshold = \ 105 options.l1_retries, 106 fixed_timeout_latency = \ 107 options.timeout_latency, 108 dynamic_timeout_enabled = \ 109 not options.disable_dyn_timeouts, 110 no_mig_atomic = not \ 111 options.allow_atomic_migration, 112 send_evictions = ( 113 options.cpu_type == "detailed"), 114 transitions_per_cycle = options.ports, 115 clk_domain=system.cpu[i].clk_domain, 116 ruby_system = ruby_system) 117 118 cpu_seq = RubySequencer(version = i, 119 icache = l1i_cache, 120 dcache = l1d_cache, 121 clk_domain=system.cpu[i].clk_domain, 122 ruby_system = ruby_system) 123 124 l1_cntrl.sequencer = cpu_seq 125 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 126 127 # Add controllers and sequencers to the appropriate lists 128 cpu_sequencers.append(cpu_seq) 129 l1_cntrl_nodes.append(l1_cntrl) 130 131 # Connect the L1 controllers and the network 132 l1_cntrl.requestFromL1Cache = ruby_system.network.slave 133 l1_cntrl.responseFromL1Cache = ruby_system.network.slave 134 l1_cntrl.persistentFromL1Cache = ruby_system.network.slave 135 136 l1_cntrl.requestToL1Cache = ruby_system.network.master 137 l1_cntrl.responseToL1Cache = ruby_system.network.master 138 l1_cntrl.persistentToL1Cache = ruby_system.network.master 139 140 141 l2_index_start = block_size_bits + l2_bits 142 143 for i in xrange(options.num_l2caches): 144 # 145 # First create the Ruby objects associated with this cpu 146 # 147 l2_cache = L2Cache(size = options.l2_size, 148 assoc = options.l2_assoc, 149 start_index_bit = l2_index_start) 150 151 l2_cntrl = L2Cache_Controller(version = i, 152 L2cache = l2_cache, 153 N_tokens = n_tokens, 154 transitions_per_cycle = options.ports, 155 ruby_system = ruby_system) 156 157 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 158 l2_cntrl_nodes.append(l2_cntrl) 159 160 # Connect the L2 controllers and the network 161 l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave 162 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 163 l2_cntrl.responseFromL2Cache = ruby_system.network.slave 164 165 l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master 166 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 167 l2_cntrl.responseToL2Cache = ruby_system.network.master 168 l2_cntrl.persistentToL2Cache = ruby_system.network.master 169 170 171 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 172 assert(phys_mem_size % options.num_dirs == 0) 173 mem_module_size = phys_mem_size / options.num_dirs 174 175 # Run each of the ruby memory controllers at a ratio of the frequency of 176 # the ruby system 177 # clk_divider value is a fix to pass regression. 178 ruby_system.memctrl_clk_domain = DerivedClockDomain( 179 clk_domain=ruby_system.clk_domain, 180 clk_divider=3) 181 182 for i in xrange(options.num_dirs): 183 dir_size = MemorySize('0B') 184 dir_size.value = mem_module_size 185 186 dir_cntrl = Directory_Controller(version = i, 187 directory = RubyDirectoryMemory( 188 version = i, size = dir_size), 189 l2_select_num_bits = l2_bits, 190 transitions_per_cycle = options.ports, 191 ruby_system = ruby_system) 192 193 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 194 dir_cntrl_nodes.append(dir_cntrl) 195 196 # Connect the directory controllers and the network 197 dir_cntrl.requestToDir = ruby_system.network.master 198 dir_cntrl.responseToDir = ruby_system.network.master 199 dir_cntrl.persistentToDir = ruby_system.network.master 200 dir_cntrl.dmaRequestToDir = ruby_system.network.master 201 202 dir_cntrl.requestFromDir = ruby_system.network.slave 203 dir_cntrl.responseFromDir = ruby_system.network.slave 204 dir_cntrl.persistentFromDir = ruby_system.network.slave 205 dir_cntrl.dmaResponseFromDir = ruby_system.network.slave 206 207 208 for i, dma_port in enumerate(dma_ports): 209 # 210 # Create the Ruby objects associated with the dma controller 211 # 212 dma_seq = DMASequencer(version = i, 213 ruby_system = ruby_system, 214 slave = dma_port) 215 216 dma_cntrl = DMA_Controller(version = i, 217 dma_sequencer = dma_seq, 218 transitions_per_cycle = options.ports, 219 ruby_system = ruby_system) 220 221 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 222 dma_cntrl_nodes.append(dma_cntrl) 223 224 # Connect the dma controller to the network 225 dma_cntrl.responseFromDir = ruby_system.network.master 226 dma_cntrl.reqToDirectory = ruby_system.network.slave 227 228 all_cntrls = l1_cntrl_nodes + \ 229 l2_cntrl_nodes + \ 230 dir_cntrl_nodes + \ 231 dma_cntrl_nodes 232 233 # Create the io controller and the sequencer 234 if full_system: 235 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 236 ruby_system._io_port = io_seq 237 io_controller = DMA_Controller(version = len(dma_ports), 238 dma_sequencer = io_seq, 239 ruby_system = ruby_system) 240 ruby_system.io_controller = io_controller 241 242 # Connect the dma controller to the network 243 io_controller.responseFromDir = ruby_system.network.master 244 io_controller.reqToDirectory = ruby_system.network.slave 245 246 all_cntrls = all_cntrls + [io_controller] 247 248 249 topology = create_topology(all_cntrls, options) 250 return (cpu_sequencers, dir_cntrl_nodes, topology) 251