MOESI_CMP_token.py revision 10524
16908SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26908SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36908SBrad.Beckmann@amd.com# All rights reserved. 46908SBrad.Beckmann@amd.com# 56908SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66908SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76908SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86908SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96908SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106908SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116908SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126908SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136908SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146908SBrad.Beckmann@amd.com# this software without specific prior written permission. 156908SBrad.Beckmann@amd.com# 166908SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176908SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186908SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196908SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206908SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216908SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226908SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236908SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246908SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256908SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266908SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276908SBrad.Beckmann@amd.com# 286908SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296908SBrad.Beckmann@amd.com 306908SBrad.Beckmann@amd.comimport math 316908SBrad.Beckmann@amd.comimport m5 326908SBrad.Beckmann@amd.comfrom m5.objects import * 336908SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 349100SBrad.Beckmann@amd.comfrom Ruby import create_topology 356908SBrad.Beckmann@amd.com 366908SBrad.Beckmann@amd.com# 376908SBrad.Beckmann@amd.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 386908SBrad.Beckmann@amd.com# 396908SBrad.Beckmann@amd.comclass L1Cache(RubyCache): 407551SBrad.Beckmann@amd.com latency = 2 416908SBrad.Beckmann@amd.com 426908SBrad.Beckmann@amd.com# 436908SBrad.Beckmann@amd.com# Note: the L2 Cache latency is not currently used 446908SBrad.Beckmann@amd.com# 456908SBrad.Beckmann@amd.comclass L2Cache(RubyCache): 467551SBrad.Beckmann@amd.com latency = 10 476908SBrad.Beckmann@amd.com 487538SBrad.Beckmann@amd.comdef define_options(parser): 497539SBrad.Beckmann@amd.com parser.add_option("--l1-retries", type="int", default=1, 507539SBrad.Beckmann@amd.com help="Token_CMP: # of l1 retries before going persistent") 517539SBrad.Beckmann@amd.com parser.add_option("--timeout-latency", type="int", default=300, 527539SBrad.Beckmann@amd.com help="Token_CMP: cycles until issuing again"); 537539SBrad.Beckmann@amd.com parser.add_option("--disable-dyn-timeouts", action="store_true", 547539SBrad.Beckmann@amd.com help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 557561SBrad.Beckmann@amd.com parser.add_option("--allow-atomic-migration", action="store_true", 567561SBrad.Beckmann@amd.com help="allow migratory sharing for atomic only accessed blocks") 577561SBrad.Beckmann@amd.com 5810519Snilay@cs.wisc.edudef create_system(options, full_system, system, dma_ports, ruby_system): 596908SBrad.Beckmann@amd.com 606908SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 616908SBrad.Beckmann@amd.com panic("This script requires the MOESI_CMP_token protocol to be built.") 626908SBrad.Beckmann@amd.com 636908SBrad.Beckmann@amd.com # 646908SBrad.Beckmann@amd.com # number of tokens that the owner passes to requests so that shared blocks can 656908SBrad.Beckmann@amd.com # respond to read requests 666908SBrad.Beckmann@amd.com # 676908SBrad.Beckmann@amd.com n_tokens = options.num_cpus + 1 686908SBrad.Beckmann@amd.com 696908SBrad.Beckmann@amd.com cpu_sequencers = [] 706908SBrad.Beckmann@amd.com 716908SBrad.Beckmann@amd.com # 726908SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 736908SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 746908SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 756908SBrad.Beckmann@amd.com # 766908SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 776908SBrad.Beckmann@amd.com l2_cntrl_nodes = [] 786908SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 796908SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 806908SBrad.Beckmann@amd.com 816908SBrad.Beckmann@amd.com # 826908SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 836908SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 846908SBrad.Beckmann@amd.com # 857564SBrad.Beckmann@amd.com l2_bits = int(math.log(options.num_l2caches, 2)) 868180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 876908SBrad.Beckmann@amd.com 886908SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 896908SBrad.Beckmann@amd.com # 906908SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 916908SBrad.Beckmann@amd.com # 926908SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 938180SBrad.Beckmann@amd.com assoc = options.l1i_assoc, 948180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 956908SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 968180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 978180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 986908SBrad.Beckmann@amd.com 996908SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, 1009695Snilay@cs.wisc.edu L1Icache = l1i_cache, 1019695Snilay@cs.wisc.edu L1Dcache = l1d_cache, 1027564SBrad.Beckmann@amd.com l2_select_num_bits = l2_bits, 1037539SBrad.Beckmann@amd.com N_tokens = n_tokens, 1047541SBrad.Beckmann@amd.com retry_threshold = \ 1057541SBrad.Beckmann@amd.com options.l1_retries, 1067539SBrad.Beckmann@amd.com fixed_timeout_latency = \ 1077539SBrad.Beckmann@amd.com options.timeout_latency, 1087539SBrad.Beckmann@amd.com dynamic_timeout_enabled = \ 1097561SBrad.Beckmann@amd.com not options.disable_dyn_timeouts, 1107561SBrad.Beckmann@amd.com no_mig_atomic = not \ 1118436SBrad.Beckmann@amd.com options.allow_atomic_migration, 1128717Snilay@cs.wisc.edu send_evictions = ( 1138717Snilay@cs.wisc.edu options.cpu_type == "detailed"), 1149841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 11510300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 1168436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1177539SBrad.Beckmann@amd.com 1188322Ssteve.reinhardt@amd.com cpu_seq = RubySequencer(version = i, 1198322Ssteve.reinhardt@amd.com icache = l1i_cache, 1208322Ssteve.reinhardt@amd.com dcache = l1d_cache, 12110300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 1228436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1238322Ssteve.reinhardt@amd.com 1248322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 12510116Snilay@cs.wisc.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 1268322Ssteve.reinhardt@amd.com 1276908SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1286908SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1296908SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1306908SBrad.Beckmann@amd.com 13110311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 13210311Snilay@cs.wisc.edu l1_cntrl.requestFromL1Cache = ruby_system.network.slave 13310311Snilay@cs.wisc.edu l1_cntrl.responseFromL1Cache = ruby_system.network.slave 13410311Snilay@cs.wisc.edu l1_cntrl.persistentFromL1Cache = ruby_system.network.slave 13510311Snilay@cs.wisc.edu 13610311Snilay@cs.wisc.edu l1_cntrl.requestToL1Cache = ruby_system.network.master 13710311Snilay@cs.wisc.edu l1_cntrl.responseToL1Cache = ruby_system.network.master 13810311Snilay@cs.wisc.edu l1_cntrl.persistentToL1Cache = ruby_system.network.master 13910311Snilay@cs.wisc.edu 14010311Snilay@cs.wisc.edu 1418180SBrad.Beckmann@amd.com l2_index_start = block_size_bits + l2_bits 1428180SBrad.Beckmann@amd.com 1436908SBrad.Beckmann@amd.com for i in xrange(options.num_l2caches): 1446908SBrad.Beckmann@amd.com # 1456908SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 1466908SBrad.Beckmann@amd.com # 1476908SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 1487564SBrad.Beckmann@amd.com assoc = options.l2_assoc, 1498180SBrad.Beckmann@amd.com start_index_bit = l2_index_start) 1506908SBrad.Beckmann@amd.com 1516908SBrad.Beckmann@amd.com l2_cntrl = L2Cache_Controller(version = i, 1529695Snilay@cs.wisc.edu L2cache = l2_cache, 1538436SBrad.Beckmann@amd.com N_tokens = n_tokens, 1549841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1558436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1566908SBrad.Beckmann@amd.com 1579468Smalek.musleh@gmail.com exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1586908SBrad.Beckmann@amd.com l2_cntrl_nodes.append(l2_cntrl) 1598257SBrad.Beckmann@amd.com 16010311Snilay@cs.wisc.edu # Connect the L2 controllers and the network 16110311Snilay@cs.wisc.edu l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave 16210311Snilay@cs.wisc.edu l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 16310311Snilay@cs.wisc.edu l2_cntrl.responseFromL2Cache = ruby_system.network.slave 16410311Snilay@cs.wisc.edu 16510311Snilay@cs.wisc.edu l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master 16610311Snilay@cs.wisc.edu l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 16710311Snilay@cs.wisc.edu l2_cntrl.responseToL2Cache = ruby_system.network.master 16810311Snilay@cs.wisc.edu l2_cntrl.persistentToL2Cache = ruby_system.network.master 16910311Snilay@cs.wisc.edu 17010311Snilay@cs.wisc.edu 1719826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1729798Snilay@cs.wisc.edu assert(phys_mem_size % options.num_dirs == 0) 1736908SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1746908SBrad.Beckmann@amd.com 1759793Sakash.bagdia@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 1769793Sakash.bagdia@arm.com # the ruby system 1779793Sakash.bagdia@arm.com # clk_divider value is a fix to pass regression. 1789793Sakash.bagdia@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 1799793Sakash.bagdia@arm.com clk_domain=ruby_system.clk_domain, 1809793Sakash.bagdia@arm.com clk_divider=3) 1819793Sakash.bagdia@arm.com 1826908SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1836908SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1846908SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1856908SBrad.Beckmann@amd.com 1866908SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 18710524Snilay@cs.wisc.edu directory = RubyDirectoryMemory( 18810524Snilay@cs.wisc.edu version = i, size = dir_size), 1898436SBrad.Beckmann@amd.com l2_select_num_bits = l2_bits, 1909841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1918436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1926908SBrad.Beckmann@amd.com 1939468Smalek.musleh@gmail.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1946908SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1956908SBrad.Beckmann@amd.com 19610311Snilay@cs.wisc.edu # Connect the directory controllers and the network 19710311Snilay@cs.wisc.edu dir_cntrl.requestToDir = ruby_system.network.master 19810311Snilay@cs.wisc.edu dir_cntrl.responseToDir = ruby_system.network.master 19910311Snilay@cs.wisc.edu dir_cntrl.persistentToDir = ruby_system.network.master 20010311Snilay@cs.wisc.edu dir_cntrl.dmaRequestToDir = ruby_system.network.master 20110311Snilay@cs.wisc.edu 20210311Snilay@cs.wisc.edu dir_cntrl.requestFromDir = ruby_system.network.slave 20310311Snilay@cs.wisc.edu dir_cntrl.responseFromDir = ruby_system.network.slave 20410311Snilay@cs.wisc.edu dir_cntrl.persistentFromDir = ruby_system.network.slave 20510311Snilay@cs.wisc.edu dir_cntrl.dmaResponseFromDir = ruby_system.network.slave 20610311Snilay@cs.wisc.edu 20710311Snilay@cs.wisc.edu 2088929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 2096908SBrad.Beckmann@amd.com # 2106908SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 2116908SBrad.Beckmann@amd.com # 2126908SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 21310519Snilay@cs.wisc.edu ruby_system = ruby_system, 21410519Snilay@cs.wisc.edu slave = dma_port) 2156908SBrad.Beckmann@amd.com 2166908SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 2178477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 2189841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 2198477Snilay@cs.wisc.edu ruby_system = ruby_system) 2206908SBrad.Beckmann@amd.com 2219468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 2226908SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 2238257SBrad.Beckmann@amd.com 22410519Snilay@cs.wisc.edu # Connect the dma controller to the network 22510519Snilay@cs.wisc.edu dma_cntrl.responseFromDir = ruby_system.network.master 22610519Snilay@cs.wisc.edu dma_cntrl.reqToDirectory = ruby_system.network.slave 22710519Snilay@cs.wisc.edu 2286908SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + \ 2296908SBrad.Beckmann@amd.com l2_cntrl_nodes + \ 2306908SBrad.Beckmann@amd.com dir_cntrl_nodes + \ 2316908SBrad.Beckmann@amd.com dma_cntrl_nodes 2326908SBrad.Beckmann@amd.com 23310519Snilay@cs.wisc.edu # Create the io controller and the sequencer 23410519Snilay@cs.wisc.edu if full_system: 23510519Snilay@cs.wisc.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 23610519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 23710519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 23810519Snilay@cs.wisc.edu dma_sequencer = io_seq, 23910519Snilay@cs.wisc.edu ruby_system = ruby_system) 24010519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 24110519Snilay@cs.wisc.edu 24210519Snilay@cs.wisc.edu # Connect the dma controller to the network 24310519Snilay@cs.wisc.edu io_controller.responseFromDir = ruby_system.network.master 24410519Snilay@cs.wisc.edu io_controller.reqToDirectory = ruby_system.network.slave 24510519Snilay@cs.wisc.edu 24610519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 24710519Snilay@cs.wisc.edu 24810519Snilay@cs.wisc.edu 2499100SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 2509100SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, topology) 251