MOESI_CMP_directory.py revision 7535:7f8213cb2337
113991Sandreas.sandberg@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 29288Sandreas.hansson@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 39288Sandreas.hansson@arm.com# All rights reserved. 49288Sandreas.hansson@arm.com# 59288Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 69288Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 79288Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 89288Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 99288Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 109288Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 119288Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 129288Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 139288Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 149288Sandreas.hansson@arm.com# this software without specific prior written permission. 159288Sandreas.hansson@arm.com# 169288Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179288Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189288Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199288Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209288Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219288Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229288Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239288Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249288Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259288Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269288Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279288Sandreas.hansson@arm.com# 289288Sandreas.hansson@arm.com# Authors: Brad Beckmann 299288Sandreas.hansson@arm.com 309288Sandreas.hansson@arm.comimport math 319288Sandreas.hansson@arm.comimport m5 329288Sandreas.hansson@arm.comfrom m5.objects import * 339288Sandreas.hansson@arm.comfrom m5.defines import buildEnv 349288Sandreas.hansson@arm.com 359288Sandreas.hansson@arm.com# 369288Sandreas.hansson@arm.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 379288Sandreas.hansson@arm.com# 389288Sandreas.hansson@arm.comclass L1Cache(RubyCache): 399288Sandreas.hansson@arm.com latency = 3 4010623Smitch.hayenga@arm.com 419288Sandreas.hansson@arm.com# 4213416Sjavier.bueno@metempsy.com# Note: the L2 Cache latency is not currently used 438831Smrinmoy.ghosh@arm.com# 448832SAli.Saidi@ARM.comclass L2Cache(RubyCache): 4513665Sandreas.sandberg@arm.com latency = 15 4613665Sandreas.sandberg@arm.com 4713665Sandreas.sandberg@arm.comdef create_system(options, phys_mem, piobus, dma_devices): 4813665Sandreas.sandberg@arm.com 498832SAli.Saidi@ARM.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': 5013416Sjavier.bueno@metempsy.com panic("This script requires the MOESI_CMP_directory protocol to be built.") 5113416Sjavier.bueno@metempsy.com 5213416Sjavier.bueno@metempsy.com cpu_sequencers = [] 5313416Sjavier.bueno@metempsy.com 5413416Sjavier.bueno@metempsy.com # 5513416Sjavier.bueno@metempsy.com # The ruby network creation expects the list of nodes in the system to be 5613416Sjavier.bueno@metempsy.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 5713416Sjavier.bueno@metempsy.com # listed before the directory nodes and directory nodes before dma nodes, etc. 5813416Sjavier.bueno@metempsy.com # 5913416Sjavier.bueno@metempsy.com l1_cntrl_nodes = [] 6013416Sjavier.bueno@metempsy.com l2_cntrl_nodes = [] 6113416Sjavier.bueno@metempsy.com dir_cntrl_nodes = [] 629288Sandreas.hansson@arm.com dma_cntrl_nodes = [] 638831Smrinmoy.ghosh@arm.com 648831Smrinmoy.ghosh@arm.com # 659338SAndreas.Sandberg@arm.com # Must create the individual controllers before the network to ensure the 6613416Sjavier.bueno@metempsy.com # controller constructors are called before the network constructor 6713416Sjavier.bueno@metempsy.com # 6813416Sjavier.bueno@metempsy.com 6910466Sandreas.hansson@arm.com for i in xrange(options.num_cpus): 708831Smrinmoy.ghosh@arm.com # 7113422Sodanrc@yahoo.com.br # First create the Ruby objects associated with this cpu 7213422Sodanrc@yahoo.com.br # 7313422Sodanrc@yahoo.com.br l1i_cache = L1Cache(size = options.l1i_size, 7410623Smitch.hayenga@arm.com assoc = options.l1i_assoc) 7510623Smitch.hayenga@arm.com l1d_cache = L1Cache(size = options.l1d_size, 7610623Smitch.hayenga@arm.com assoc = options.l1d_assoc) 7710623Smitch.hayenga@arm.com 7810623Smitch.hayenga@arm.com cpu_seq = RubySequencer(version = i, 7913416Sjavier.bueno@metempsy.com icache = l1i_cache, 8013416Sjavier.bueno@metempsy.com dcache = l1d_cache, 8113551Sjavier.bueno@metempsy.com physMemPort = phys_mem.port, 8213551Sjavier.bueno@metempsy.com physmem = phys_mem) 8313416Sjavier.bueno@metempsy.com 8413416Sjavier.bueno@metempsy.com if piobus != None: 8513416Sjavier.bueno@metempsy.com cpu_seq.pio_port = piobus.port 8613416Sjavier.bueno@metempsy.com 8713416Sjavier.bueno@metempsy.com l1_cntrl = L1Cache_Controller(version = i, 8813416Sjavier.bueno@metempsy.com sequencer = cpu_seq, 8913416Sjavier.bueno@metempsy.com L1IcacheMemory = l1i_cache, 9013416Sjavier.bueno@metempsy.com L1DcacheMemory = l1d_cache, 9113416Sjavier.bueno@metempsy.com l2_select_num_bits = \ 9213416Sjavier.bueno@metempsy.com math.log(options.num_l2caches, 2)) 9313416Sjavier.bueno@metempsy.com # 9413416Sjavier.bueno@metempsy.com # Add controllers and sequencers to the appropriate lists 9513416Sjavier.bueno@metempsy.com # 9613416Sjavier.bueno@metempsy.com cpu_sequencers.append(cpu_seq) 9713416Sjavier.bueno@metempsy.com l1_cntrl_nodes.append(l1_cntrl) 9813416Sjavier.bueno@metempsy.com 9913416Sjavier.bueno@metempsy.com for i in xrange(options.num_l2caches): 10013416Sjavier.bueno@metempsy.com # 10110623Smitch.hayenga@arm.com # First create the Ruby objects associated with this cpu 10213991Sandreas.sandberg@arm.com # 10313991Sandreas.sandberg@arm.com l2_cache = L2Cache(size = options.l2_size, 10413991Sandreas.sandberg@arm.com assoc = options.l2_assoc) 10513991Sandreas.sandberg@arm.com 10613991Sandreas.sandberg@arm.com l2_cntrl = L2Cache_Controller(version = i, 10713991Sandreas.sandberg@arm.com L2cacheMemory = l2_cache) 10813991Sandreas.sandberg@arm.com 10910623Smitch.hayenga@arm.com l2_cntrl_nodes.append(l2_cntrl) 11010623Smitch.hayenga@arm.com 11110623Smitch.hayenga@arm.com phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1 11210623Smitch.hayenga@arm.com mem_module_size = phys_mem_size / options.num_dirs 11310623Smitch.hayenga@arm.com 11410623Smitch.hayenga@arm.com for i in xrange(options.num_dirs): 11510623Smitch.hayenga@arm.com # 11610623Smitch.hayenga@arm.com # Create the Ruby objects associated with the directory controller 11710623Smitch.hayenga@arm.com # 11810623Smitch.hayenga@arm.com 11910623Smitch.hayenga@arm.com mem_cntrl = RubyMemoryControl(version = i) 12010623Smitch.hayenga@arm.com 12110623Smitch.hayenga@arm.com dir_size = MemorySize('0B') 12210623Smitch.hayenga@arm.com dir_size.value = mem_module_size 1238831Smrinmoy.ghosh@arm.com 1248831Smrinmoy.ghosh@arm.com dir_cntrl = Directory_Controller(version = i, 1259338SAndreas.Sandberg@arm.com directory = \ 1268831Smrinmoy.ghosh@arm.com RubyDirectoryMemory(version = i, 12713422Sodanrc@yahoo.com.br size = dir_size), 12813422Sodanrc@yahoo.com.br memBuffer = mem_cntrl) 12913422Sodanrc@yahoo.com.br 13010623Smitch.hayenga@arm.com dir_cntrl_nodes.append(dir_cntrl) 13110623Smitch.hayenga@arm.com 13210623Smitch.hayenga@arm.com for i, dma_device in enumerate(dma_devices): 13310623Smitch.hayenga@arm.com # 13410623Smitch.hayenga@arm.com # Create the Ruby objects associated with the dma controller 13510623Smitch.hayenga@arm.com # 13610623Smitch.hayenga@arm.com dma_seq = DMASequencer(version = i, 13710623Smitch.hayenga@arm.com physMemPort = phys_mem.port, 13810623Smitch.hayenga@arm.com physmem = phys_mem) 13910623Smitch.hayenga@arm.com 14010623Smitch.hayenga@arm.com dma_cntrl = DMA_Controller(version = i, 14113427Sodanrc@yahoo.com.br dma_sequencer = dma_seq) 14213427Sodanrc@yahoo.com.br 14313427Sodanrc@yahoo.com.br dma_cntrl.dma_sequencer.port = dma_device.dma 14413427Sodanrc@yahoo.com.br dma_cntrl_nodes.append(dma_cntrl) 14510623Smitch.hayenga@arm.com 1468831Smrinmoy.ghosh@arm.com all_cntrls = l1_cntrl_nodes + \ 1478831Smrinmoy.ghosh@arm.com l2_cntrl_nodes + \ 1489338SAndreas.Sandberg@arm.com dir_cntrl_nodes + \ 1498831Smrinmoy.ghosh@arm.com dma_cntrl_nodes 15010623Smitch.hayenga@arm.com 15113553Sjavier.bueno@metempsy.com return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 15213772Sjavier.bueno@metempsy.com