MOESI_CMP_directory.py revision 11266:452e10b868ea
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35from Ruby import send_evicts 36 37# 38# Declare caches used by the protocol 39# 40class L1Cache(RubyCache): pass 41class L2Cache(RubyCache): pass 42 43def define_options(parser): 44 return 45 46def create_system(options, full_system, system, dma_ports, ruby_system): 47 48 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': 49 panic("This script requires the MOESI_CMP_directory protocol to be built.") 50 51 cpu_sequencers = [] 52 53 # 54 # The ruby network creation expects the list of nodes in the system to be 55 # consistent with the NetDest list. Therefore the l1 controller nodes must be 56 # listed before the directory nodes and directory nodes before dma nodes, etc. 57 # 58 l1_cntrl_nodes = [] 59 l2_cntrl_nodes = [] 60 dir_cntrl_nodes = [] 61 dma_cntrl_nodes = [] 62 63 # 64 # Must create the individual controllers before the network to ensure the 65 # controller constructors are called before the network constructor 66 # 67 l2_bits = int(math.log(options.num_l2caches, 2)) 68 block_size_bits = int(math.log(options.cacheline_size, 2)) 69 70 for i in xrange(options.num_cpus): 71 # 72 # First create the Ruby objects associated with this cpu 73 # 74 l1i_cache = L1Cache(size = options.l1i_size, 75 assoc = options.l1i_assoc, 76 start_index_bit = block_size_bits, 77 is_icache = True) 78 l1d_cache = L1Cache(size = options.l1d_size, 79 assoc = options.l1d_assoc, 80 start_index_bit = block_size_bits, 81 is_icache = False) 82 83 # the ruby random tester reuses num_cpus to specify the 84 # number of cpu ports connected to the tester object, which 85 # is stored in system.cpu. because there is only ever one 86 # tester object, num_cpus is not necessarily equal to the 87 # size of system.cpu; therefore if len(system.cpu) == 1 88 # we use system.cpu[0] to set the clk_domain, thereby ensuring 89 # we don't index off the end of the cpu list. 90 if len(system.cpu) == 1: 91 clk_domain = system.cpu[0].clk_domain 92 else: 93 clk_domain = system.cpu[i].clk_domain 94 95 l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache, 96 L1Dcache=l1d_cache, 97 l2_select_num_bits=l2_bits, 98 send_evictions=send_evicts(options), 99 transitions_per_cycle=options.ports, 100 clk_domain=clk_domain, 101 ruby_system=ruby_system) 102 103 cpu_seq = RubySequencer(version=i, icache=l1i_cache, 104 dcache=l1d_cache, clk_domain=clk_domain, 105 ruby_system=ruby_system) 106 107 l1_cntrl.sequencer = cpu_seq 108 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 109 110 # Add controllers and sequencers to the appropriate lists 111 cpu_sequencers.append(cpu_seq) 112 l1_cntrl_nodes.append(l1_cntrl) 113 114 # Connect the L1 controllers and the network 115 l1_cntrl.mandatoryQueue = MessageBuffer() 116 l1_cntrl.requestFromL1Cache = MessageBuffer() 117 l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave 118 l1_cntrl.responseFromL1Cache = MessageBuffer() 119 l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave 120 l1_cntrl.requestToL1Cache = MessageBuffer() 121 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 122 l1_cntrl.responseToL1Cache = MessageBuffer() 123 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 124 l1_cntrl.triggerQueue = MessageBuffer(ordered = True) 125 126 127 l2_index_start = block_size_bits + l2_bits 128 129 for i in xrange(options.num_l2caches): 130 # 131 # First create the Ruby objects associated with this cpu 132 # 133 l2_cache = L2Cache(size = options.l2_size, 134 assoc = options.l2_assoc, 135 start_index_bit = l2_index_start) 136 137 l2_cntrl = L2Cache_Controller(version = i, 138 L2cache = l2_cache, 139 transitions_per_cycle = options.ports, 140 ruby_system = ruby_system) 141 142 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 143 l2_cntrl_nodes.append(l2_cntrl) 144 145 # Connect the L2 controllers and the network 146 l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() 147 l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave 148 l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 149 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 150 l2_cntrl.responseFromL2Cache = MessageBuffer() 151 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 152 153 l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() 154 l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master 155 l2_cntrl.L1RequestToL2Cache = MessageBuffer() 156 l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 157 l2_cntrl.responseToL2Cache = MessageBuffer() 158 l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 159 l2_cntrl.triggerQueue = MessageBuffer(ordered = True) 160 161 162 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 163 assert(phys_mem_size % options.num_dirs == 0) 164 mem_module_size = phys_mem_size / options.num_dirs 165 166 167 # Run each of the ruby memory controllers at a ratio of the frequency of 168 # the ruby system. 169 # clk_divider value is a fix to pass regression. 170 ruby_system.memctrl_clk_domain = DerivedClockDomain( 171 clk_domain=ruby_system.clk_domain, 172 clk_divider=3) 173 174 for i in xrange(options.num_dirs): 175 dir_size = MemorySize('0B') 176 dir_size.value = mem_module_size 177 178 dir_cntrl = Directory_Controller(version = i, 179 directory = RubyDirectoryMemory( 180 version = i, size = dir_size), 181 transitions_per_cycle = options.ports, 182 ruby_system = ruby_system) 183 184 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 185 dir_cntrl_nodes.append(dir_cntrl) 186 187 # Connect the directory controllers and the network 188 dir_cntrl.requestToDir = MessageBuffer() 189 dir_cntrl.requestToDir.slave = ruby_system.network.master 190 dir_cntrl.responseToDir = MessageBuffer() 191 dir_cntrl.responseToDir.slave = ruby_system.network.master 192 dir_cntrl.responseFromDir = MessageBuffer() 193 dir_cntrl.responseFromDir.master = ruby_system.network.slave 194 dir_cntrl.forwardFromDir = MessageBuffer() 195 dir_cntrl.forwardFromDir.master = ruby_system.network.slave 196 dir_cntrl.responseFromMemory = MessageBuffer() 197 198 199 for i, dma_port in enumerate(dma_ports): 200 # 201 # Create the Ruby objects associated with the dma controller 202 # 203 dma_seq = DMASequencer(version = i, 204 ruby_system = ruby_system, 205 slave = dma_port) 206 207 dma_cntrl = DMA_Controller(version = i, 208 dma_sequencer = dma_seq, 209 transitions_per_cycle = options.ports, 210 ruby_system = ruby_system) 211 212 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 213 dma_cntrl_nodes.append(dma_cntrl) 214 215 # Connect the dma controller to the network 216 dma_cntrl.mandatoryQueue = MessageBuffer() 217 dma_cntrl.responseFromDir = MessageBuffer() 218 dma_cntrl.responseFromDir.slave = ruby_system.network.master 219 dma_cntrl.reqToDir = MessageBuffer() 220 dma_cntrl.reqToDir.master = ruby_system.network.slave 221 dma_cntrl.respToDir = MessageBuffer() 222 dma_cntrl.respToDir.master = ruby_system.network.slave 223 dma_cntrl.triggerQueue = MessageBuffer(ordered = True) 224 225 226 all_cntrls = l1_cntrl_nodes + \ 227 l2_cntrl_nodes + \ 228 dir_cntrl_nodes + \ 229 dma_cntrl_nodes 230 231 # Create the io controller and the sequencer 232 if full_system: 233 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 234 ruby_system._io_port = io_seq 235 io_controller = DMA_Controller(version = len(dma_ports), 236 dma_sequencer = io_seq, 237 ruby_system = ruby_system) 238 ruby_system.io_controller = io_controller 239 240 # Connect the dma controller to the network 241 io_controller.mandatoryQueue = MessageBuffer() 242 io_controller.responseFromDir = MessageBuffer() 243 io_controller.responseFromDir.slave = ruby_system.network.master 244 io_controller.reqToDir = MessageBuffer() 245 io_controller.reqToDir.master = ruby_system.network.slave 246 io_controller.respToDir = MessageBuffer() 247 io_controller.respToDir.master = ruby_system.network.slave 248 io_controller.triggerQueue = MessageBuffer(ordered = True) 249 250 all_cntrls = all_cntrls + [io_controller] 251 252 253 ruby_system.network.number_of_virtual_networks = 3 254 topology = create_topology(all_cntrls, options) 255 return (cpu_sequencers, dir_cntrl_nodes, topology) 256