MOESI_CMP_directory.py revision 10300
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35 36# 37# Note: the L1 Cache latency is only used by the sequencer on fast path hits 38# 39class L1Cache(RubyCache): 40 latency = 3 41 42# 43# Note: the L2 Cache latency is not currently used 44# 45class L2Cache(RubyCache): 46 latency = 15 47 48def define_options(parser): 49 return 50 51def create_system(options, system, dma_ports, ruby_system): 52 53 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': 54 panic("This script requires the MOESI_CMP_directory protocol to be built.") 55 56 cpu_sequencers = [] 57 58 # 59 # The ruby network creation expects the list of nodes in the system to be 60 # consistent with the NetDest list. Therefore the l1 controller nodes must be 61 # listed before the directory nodes and directory nodes before dma nodes, etc. 62 # 63 l1_cntrl_nodes = [] 64 l2_cntrl_nodes = [] 65 dir_cntrl_nodes = [] 66 dma_cntrl_nodes = [] 67 68 # 69 # Must create the individual controllers before the network to ensure the 70 # controller constructors are called before the network constructor 71 # 72 l2_bits = int(math.log(options.num_l2caches, 2)) 73 block_size_bits = int(math.log(options.cacheline_size, 2)) 74 75 for i in xrange(options.num_cpus): 76 # 77 # First create the Ruby objects associated with this cpu 78 # 79 l1i_cache = L1Cache(size = options.l1i_size, 80 assoc = options.l1i_assoc, 81 start_index_bit = block_size_bits, 82 is_icache = True) 83 l1d_cache = L1Cache(size = options.l1d_size, 84 assoc = options.l1d_assoc, 85 start_index_bit = block_size_bits, 86 is_icache = False) 87 88 l1_cntrl = L1Cache_Controller(version = i, 89 L1Icache = l1i_cache, 90 L1Dcache = l1d_cache, 91 l2_select_num_bits = l2_bits, 92 send_evictions = ( 93 options.cpu_type == "detailed"), 94 transitions_per_cycle = options.ports, 95 clk_domain=system.cpu[i].clk_domain, 96 ruby_system = ruby_system) 97 98 cpu_seq = RubySequencer(version = i, 99 icache = l1i_cache, 100 dcache = l1d_cache, 101 clk_domain=system.cpu[i].clk_domain, 102 ruby_system = ruby_system) 103 104 l1_cntrl.sequencer = cpu_seq 105 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 106 107 # 108 # Add controllers and sequencers to the appropriate lists 109 # 110 cpu_sequencers.append(cpu_seq) 111 l1_cntrl_nodes.append(l1_cntrl) 112 113 l2_index_start = block_size_bits + l2_bits 114 115 for i in xrange(options.num_l2caches): 116 # 117 # First create the Ruby objects associated with this cpu 118 # 119 l2_cache = L2Cache(size = options.l2_size, 120 assoc = options.l2_assoc, 121 start_index_bit = l2_index_start) 122 123 l2_cntrl = L2Cache_Controller(version = i, 124 L2cache = l2_cache, 125 transitions_per_cycle = options.ports, 126 ruby_system = ruby_system) 127 128 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 129 l2_cntrl_nodes.append(l2_cntrl) 130 131 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 132 assert(phys_mem_size % options.num_dirs == 0) 133 mem_module_size = phys_mem_size / options.num_dirs 134 135 # Run each of the ruby memory controllers at a ratio of the frequency of 136 # the ruby system. 137 # clk_divider value is a fix to pass regression. 138 ruby_system.memctrl_clk_domain = DerivedClockDomain( 139 clk_domain=ruby_system.clk_domain, 140 clk_divider=3) 141 142 for i in xrange(options.num_dirs): 143 # 144 # Create the Ruby objects associated with the directory controller 145 # 146 147 mem_cntrl = RubyMemoryControl( 148 clk_domain = ruby_system.memctrl_clk_domain, 149 version = i, 150 ruby_system = ruby_system) 151 152 dir_size = MemorySize('0B') 153 dir_size.value = mem_module_size 154 155 dir_cntrl = Directory_Controller(version = i, 156 directory = \ 157 RubyDirectoryMemory(version = i, 158 size = dir_size, 159 use_map = options.use_map), 160 memBuffer = mem_cntrl, 161 transitions_per_cycle = options.ports, 162 ruby_system = ruby_system) 163 164 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 165 dir_cntrl_nodes.append(dir_cntrl) 166 167 for i, dma_port in enumerate(dma_ports): 168 # 169 # Create the Ruby objects associated with the dma controller 170 # 171 dma_seq = DMASequencer(version = i, 172 ruby_system = ruby_system) 173 174 dma_cntrl = DMA_Controller(version = i, 175 dma_sequencer = dma_seq, 176 transitions_per_cycle = options.ports, 177 ruby_system = ruby_system) 178 179 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 180 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 181 dma_cntrl_nodes.append(dma_cntrl) 182 183 all_cntrls = l1_cntrl_nodes + \ 184 l2_cntrl_nodes + \ 185 dir_cntrl_nodes + \ 186 dma_cntrl_nodes 187 188 topology = create_topology(all_cntrls, options) 189 190 return (cpu_sequencers, dir_cntrl_nodes, topology) 191