MOESI_CMP_directory.py revision 8717
16911SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26911SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36911SBrad.Beckmann@amd.com# All rights reserved. 46911SBrad.Beckmann@amd.com# 56911SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66911SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76911SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96911SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116911SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126911SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136911SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146911SBrad.Beckmann@amd.com# this software without specific prior written permission. 156911SBrad.Beckmann@amd.com# 166911SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176911SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186911SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196911SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206911SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216911SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226911SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236911SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246911SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256911SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266911SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276911SBrad.Beckmann@amd.com# 286911SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296911SBrad.Beckmann@amd.com 306911SBrad.Beckmann@amd.comimport math 316911SBrad.Beckmann@amd.comimport m5 326911SBrad.Beckmann@amd.comfrom m5.objects import * 336911SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 346911SBrad.Beckmann@amd.com 356911SBrad.Beckmann@amd.com# 366911SBrad.Beckmann@amd.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 376911SBrad.Beckmann@amd.com# 386911SBrad.Beckmann@amd.comclass L1Cache(RubyCache): 396911SBrad.Beckmann@amd.com latency = 3 406911SBrad.Beckmann@amd.com 416911SBrad.Beckmann@amd.com# 426911SBrad.Beckmann@amd.com# Note: the L2 Cache latency is not currently used 436911SBrad.Beckmann@amd.com# 446911SBrad.Beckmann@amd.comclass L2Cache(RubyCache): 456911SBrad.Beckmann@amd.com latency = 15 466911SBrad.Beckmann@amd.com 477538SBrad.Beckmann@amd.comdef define_options(parser): 487538SBrad.Beckmann@amd.com return 497538SBrad.Beckmann@amd.com 508436SBrad.Beckmann@amd.comdef create_system(options, system, piobus, dma_devices, ruby_system): 518436SBrad.Beckmann@amd.com 526911SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': 536911SBrad.Beckmann@amd.com panic("This script requires the MOESI_CMP_directory protocol to be built.") 546911SBrad.Beckmann@amd.com 556911SBrad.Beckmann@amd.com cpu_sequencers = [] 566911SBrad.Beckmann@amd.com 576911SBrad.Beckmann@amd.com # 586911SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 596911SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 606911SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 616911SBrad.Beckmann@amd.com # 626911SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 636911SBrad.Beckmann@amd.com l2_cntrl_nodes = [] 646911SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 656911SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 666911SBrad.Beckmann@amd.com 676911SBrad.Beckmann@amd.com # 686911SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 696911SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 706911SBrad.Beckmann@amd.com # 718180SBrad.Beckmann@amd.com l2_bits = int(math.log(options.num_l2caches, 2)) 728180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 738257SBrad.Beckmann@amd.com 748257SBrad.Beckmann@amd.com cntrl_count = 0 756911SBrad.Beckmann@amd.com 766911SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 776911SBrad.Beckmann@amd.com # 786911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 796911SBrad.Beckmann@amd.com # 806911SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 818180SBrad.Beckmann@amd.com assoc = options.l1i_assoc, 828180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 836911SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 848180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 858180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 866911SBrad.Beckmann@amd.com 878322Ssteve.reinhardt@amd.com l1_cntrl = L1Cache_Controller(version = i, 888322Ssteve.reinhardt@amd.com cntrl_id = cntrl_count, 898322Ssteve.reinhardt@amd.com L1IcacheMemory = l1i_cache, 908322Ssteve.reinhardt@amd.com L1DcacheMemory = l1d_cache, 918436SBrad.Beckmann@amd.com l2_select_num_bits = l2_bits, 928717Snilay@cs.wisc.edu send_evictions = ( 938717Snilay@cs.wisc.edu options.cpu_type == "detailed"), 948436SBrad.Beckmann@amd.com ruby_system = ruby_system) 958322Ssteve.reinhardt@amd.com 967015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 977015SBrad.Beckmann@amd.com icache = l1i_cache, 986911SBrad.Beckmann@amd.com dcache = l1d_cache, 997541SBrad.Beckmann@amd.com physMemPort = system.physmem.port, 1008436SBrad.Beckmann@amd.com physmem = system.physmem, 1018436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1026911SBrad.Beckmann@amd.com 1038322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 1048322Ssteve.reinhardt@amd.com 1056911SBrad.Beckmann@amd.com if piobus != None: 1066911SBrad.Beckmann@amd.com cpu_seq.pio_port = piobus.port 1076911SBrad.Beckmann@amd.com 1087541SBrad.Beckmann@amd.com exec("system.l1_cntrl%d = l1_cntrl" % i) 1096911SBrad.Beckmann@amd.com # 1106911SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1116911SBrad.Beckmann@amd.com # 1126911SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1136911SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1146911SBrad.Beckmann@amd.com 1158257SBrad.Beckmann@amd.com cntrl_count += 1 1168257SBrad.Beckmann@amd.com 1178180SBrad.Beckmann@amd.com l2_index_start = block_size_bits + l2_bits 1188180SBrad.Beckmann@amd.com 1196911SBrad.Beckmann@amd.com for i in xrange(options.num_l2caches): 1206911SBrad.Beckmann@amd.com # 1216911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 1226911SBrad.Beckmann@amd.com # 1236911SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 1248180SBrad.Beckmann@amd.com assoc = options.l2_assoc, 1258180SBrad.Beckmann@amd.com start_index_bit = l2_index_start) 1266911SBrad.Beckmann@amd.com 1276911SBrad.Beckmann@amd.com l2_cntrl = L2Cache_Controller(version = i, 1288257SBrad.Beckmann@amd.com cntrl_id = cntrl_count, 1298436SBrad.Beckmann@amd.com L2cacheMemory = l2_cache, 1308436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1316911SBrad.Beckmann@amd.com 1327541SBrad.Beckmann@amd.com exec("system.l2_cntrl%d = l2_cntrl" % i) 1336911SBrad.Beckmann@amd.com l2_cntrl_nodes.append(l2_cntrl) 1348257SBrad.Beckmann@amd.com 1358257SBrad.Beckmann@amd.com cntrl_count += 1 1366911SBrad.Beckmann@amd.com 1377541SBrad.Beckmann@amd.com phys_mem_size = long(system.physmem.range.second) - \ 1387541SBrad.Beckmann@amd.com long(system.physmem.range.first) + 1 1396911SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1406911SBrad.Beckmann@amd.com 1416911SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1426911SBrad.Beckmann@amd.com # 1436911SBrad.Beckmann@amd.com # Create the Ruby objects associated with the directory controller 1446911SBrad.Beckmann@amd.com # 1456911SBrad.Beckmann@amd.com 1466911SBrad.Beckmann@amd.com mem_cntrl = RubyMemoryControl(version = i) 1476911SBrad.Beckmann@amd.com 1486911SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1496911SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1506911SBrad.Beckmann@amd.com 1516911SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1528257SBrad.Beckmann@amd.com cntrl_id = cntrl_count, 1536911SBrad.Beckmann@amd.com directory = \ 1546911SBrad.Beckmann@amd.com RubyDirectoryMemory(version = i, 1558436SBrad.Beckmann@amd.com size = dir_size), 1568436SBrad.Beckmann@amd.com memBuffer = mem_cntrl, 1578436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1586911SBrad.Beckmann@amd.com 1597541SBrad.Beckmann@amd.com exec("system.dir_cntrl%d = dir_cntrl" % i) 1606911SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1616911SBrad.Beckmann@amd.com 1628257SBrad.Beckmann@amd.com cntrl_count += 1 1638257SBrad.Beckmann@amd.com 1646911SBrad.Beckmann@amd.com for i, dma_device in enumerate(dma_devices): 1656911SBrad.Beckmann@amd.com # 1666911SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1676911SBrad.Beckmann@amd.com # 1686911SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1697541SBrad.Beckmann@amd.com physMemPort = system.physmem.port, 1708477Snilay@cs.wisc.edu physmem = system.physmem, 1718477Snilay@cs.wisc.edu ruby_system = ruby_system) 1726911SBrad.Beckmann@amd.com 1736911SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1748257SBrad.Beckmann@amd.com cntrl_id = cntrl_count, 1758477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 1768477Snilay@cs.wisc.edu ruby_system = ruby_system) 1776911SBrad.Beckmann@amd.com 1787541SBrad.Beckmann@amd.com exec("system.dma_cntrl%d = dma_cntrl" % i) 1797544SBrad.Beckmann@amd.com if dma_device.type == 'MemTest': 1807633SBrad.Beckmann@amd.com exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 1817544SBrad.Beckmann@amd.com else: 1827633SBrad.Beckmann@amd.com exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 1836911SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1846911SBrad.Beckmann@amd.com 1858257SBrad.Beckmann@amd.com cntrl_count += 1 1868257SBrad.Beckmann@amd.com 1876911SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + \ 1886911SBrad.Beckmann@amd.com l2_cntrl_nodes + \ 1896911SBrad.Beckmann@amd.com dir_cntrl_nodes + \ 1906911SBrad.Beckmann@amd.com dma_cntrl_nodes 1916911SBrad.Beckmann@amd.com 1926911SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 193