MOESI_CMP_directory.py revision 7633
16911SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26911SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36911SBrad.Beckmann@amd.com# All rights reserved. 46911SBrad.Beckmann@amd.com# 56911SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66911SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76911SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96911SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116911SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126911SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136911SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146911SBrad.Beckmann@amd.com# this software without specific prior written permission. 156911SBrad.Beckmann@amd.com# 166911SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176911SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186911SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196911SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206911SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216911SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226911SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236911SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246911SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256911SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266911SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276911SBrad.Beckmann@amd.com# 286911SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296911SBrad.Beckmann@amd.com 306911SBrad.Beckmann@amd.comimport math 316911SBrad.Beckmann@amd.comimport m5 326911SBrad.Beckmann@amd.comfrom m5.objects import * 336911SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 346911SBrad.Beckmann@amd.com 356911SBrad.Beckmann@amd.com# 366911SBrad.Beckmann@amd.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 376911SBrad.Beckmann@amd.com# 386911SBrad.Beckmann@amd.comclass L1Cache(RubyCache): 396911SBrad.Beckmann@amd.com latency = 3 406911SBrad.Beckmann@amd.com 416911SBrad.Beckmann@amd.com# 426911SBrad.Beckmann@amd.com# Note: the L2 Cache latency is not currently used 436911SBrad.Beckmann@amd.com# 446911SBrad.Beckmann@amd.comclass L2Cache(RubyCache): 456911SBrad.Beckmann@amd.com latency = 15 466911SBrad.Beckmann@amd.com 477538SBrad.Beckmann@amd.comdef define_options(parser): 487538SBrad.Beckmann@amd.com return 497538SBrad.Beckmann@amd.com 507541SBrad.Beckmann@amd.comdef create_system(options, system, piobus, dma_devices): 516911SBrad.Beckmann@amd.com 526911SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': 536911SBrad.Beckmann@amd.com panic("This script requires the MOESI_CMP_directory protocol to be built.") 546911SBrad.Beckmann@amd.com 556911SBrad.Beckmann@amd.com cpu_sequencers = [] 566911SBrad.Beckmann@amd.com 576911SBrad.Beckmann@amd.com # 586911SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 596911SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 606911SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 616911SBrad.Beckmann@amd.com # 626911SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 636911SBrad.Beckmann@amd.com l2_cntrl_nodes = [] 646911SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 656911SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 666911SBrad.Beckmann@amd.com 676911SBrad.Beckmann@amd.com # 686911SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 696911SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 706911SBrad.Beckmann@amd.com # 716911SBrad.Beckmann@amd.com 726911SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 736911SBrad.Beckmann@amd.com # 746911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 756911SBrad.Beckmann@amd.com # 766911SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 776911SBrad.Beckmann@amd.com assoc = options.l1i_assoc) 786911SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 796911SBrad.Beckmann@amd.com assoc = options.l1d_assoc) 806911SBrad.Beckmann@amd.com 817015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 827015SBrad.Beckmann@amd.com icache = l1i_cache, 836911SBrad.Beckmann@amd.com dcache = l1d_cache, 847541SBrad.Beckmann@amd.com physMemPort = system.physmem.port, 857541SBrad.Beckmann@amd.com physmem = system.physmem) 866911SBrad.Beckmann@amd.com 876911SBrad.Beckmann@amd.com if piobus != None: 886911SBrad.Beckmann@amd.com cpu_seq.pio_port = piobus.port 896911SBrad.Beckmann@amd.com 906911SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, 916911SBrad.Beckmann@amd.com sequencer = cpu_seq, 926911SBrad.Beckmann@amd.com L1IcacheMemory = l1i_cache, 936911SBrad.Beckmann@amd.com L1DcacheMemory = l1d_cache, 946911SBrad.Beckmann@amd.com l2_select_num_bits = \ 957541SBrad.Beckmann@amd.com math.log(options.num_l2caches, 967541SBrad.Beckmann@amd.com 2)) 977541SBrad.Beckmann@amd.com 987541SBrad.Beckmann@amd.com exec("system.l1_cntrl%d = l1_cntrl" % i) 996911SBrad.Beckmann@amd.com # 1006911SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1016911SBrad.Beckmann@amd.com # 1026911SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1036911SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1046911SBrad.Beckmann@amd.com 1056911SBrad.Beckmann@amd.com for i in xrange(options.num_l2caches): 1066911SBrad.Beckmann@amd.com # 1076911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 1086911SBrad.Beckmann@amd.com # 1096911SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 1106911SBrad.Beckmann@amd.com assoc = options.l2_assoc) 1116911SBrad.Beckmann@amd.com 1126911SBrad.Beckmann@amd.com l2_cntrl = L2Cache_Controller(version = i, 1136911SBrad.Beckmann@amd.com L2cacheMemory = l2_cache) 1146911SBrad.Beckmann@amd.com 1157541SBrad.Beckmann@amd.com exec("system.l2_cntrl%d = l2_cntrl" % i) 1166911SBrad.Beckmann@amd.com l2_cntrl_nodes.append(l2_cntrl) 1176911SBrad.Beckmann@amd.com 1187541SBrad.Beckmann@amd.com phys_mem_size = long(system.physmem.range.second) - \ 1197541SBrad.Beckmann@amd.com long(system.physmem.range.first) + 1 1206911SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1216911SBrad.Beckmann@amd.com 1226911SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1236911SBrad.Beckmann@amd.com # 1246911SBrad.Beckmann@amd.com # Create the Ruby objects associated with the directory controller 1256911SBrad.Beckmann@amd.com # 1266911SBrad.Beckmann@amd.com 1276911SBrad.Beckmann@amd.com mem_cntrl = RubyMemoryControl(version = i) 1286911SBrad.Beckmann@amd.com 1296911SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1306911SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1316911SBrad.Beckmann@amd.com 1326911SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1336911SBrad.Beckmann@amd.com directory = \ 1346911SBrad.Beckmann@amd.com RubyDirectoryMemory(version = i, 1357541SBrad.Beckmann@amd.com size = \ 1367541SBrad.Beckmann@amd.com dir_size), 1376911SBrad.Beckmann@amd.com memBuffer = mem_cntrl) 1386911SBrad.Beckmann@amd.com 1397541SBrad.Beckmann@amd.com exec("system.dir_cntrl%d = dir_cntrl" % i) 1406911SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1416911SBrad.Beckmann@amd.com 1426911SBrad.Beckmann@amd.com for i, dma_device in enumerate(dma_devices): 1436911SBrad.Beckmann@amd.com # 1446911SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1456911SBrad.Beckmann@amd.com # 1466911SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1477541SBrad.Beckmann@amd.com physMemPort = system.physmem.port, 1487541SBrad.Beckmann@amd.com physmem = system.physmem) 1496911SBrad.Beckmann@amd.com 1506911SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1516911SBrad.Beckmann@amd.com dma_sequencer = dma_seq) 1526911SBrad.Beckmann@amd.com 1537541SBrad.Beckmann@amd.com exec("system.dma_cntrl%d = dma_cntrl" % i) 1547544SBrad.Beckmann@amd.com if dma_device.type == 'MemTest': 1557633SBrad.Beckmann@amd.com exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 1567544SBrad.Beckmann@amd.com else: 1577633SBrad.Beckmann@amd.com exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 1586911SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1596911SBrad.Beckmann@amd.com 1606911SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + \ 1616911SBrad.Beckmann@amd.com l2_cntrl_nodes + \ 1626911SBrad.Beckmann@amd.com dir_cntrl_nodes + \ 1636911SBrad.Beckmann@amd.com dma_cntrl_nodes 1646911SBrad.Beckmann@amd.com 1656911SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 166