MOESI_CMP_directory.py revision 12598
16911SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26911SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36911SBrad.Beckmann@amd.com# All rights reserved. 46911SBrad.Beckmann@amd.com# 56911SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66911SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76911SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96911SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116911SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126911SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136911SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146911SBrad.Beckmann@amd.com# this software without specific prior written permission. 156911SBrad.Beckmann@amd.com# 166911SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176911SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186911SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196911SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206911SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216911SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226911SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236911SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246911SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256911SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266911SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276911SBrad.Beckmann@amd.com# 286911SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296911SBrad.Beckmann@amd.com 306911SBrad.Beckmann@amd.comimport math 316911SBrad.Beckmann@amd.comimport m5 326911SBrad.Beckmann@amd.comfrom m5.objects import * 336911SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 3412065Snikos.nikoleris@arm.comfrom Ruby import create_topology, create_directories 3510529Smorr@cs.wisc.edufrom Ruby import send_evicts 366911SBrad.Beckmann@amd.com 376911SBrad.Beckmann@amd.com# 3811019Sjthestness@gmail.com# Declare caches used by the protocol 396911SBrad.Beckmann@amd.com# 4011019Sjthestness@gmail.comclass L1Cache(RubyCache): pass 4111019Sjthestness@gmail.comclass L2Cache(RubyCache): pass 426911SBrad.Beckmann@amd.com 437538SBrad.Beckmann@amd.comdef define_options(parser): 447538SBrad.Beckmann@amd.com return 457538SBrad.Beckmann@amd.com 4612598Snikos.nikoleris@arm.comdef create_system(options, full_system, system, dma_ports, bootmem, 4712598Snikos.nikoleris@arm.com ruby_system): 488436SBrad.Beckmann@amd.com 496911SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': 506911SBrad.Beckmann@amd.com panic("This script requires the MOESI_CMP_directory protocol to be built.") 516911SBrad.Beckmann@amd.com 526911SBrad.Beckmann@amd.com cpu_sequencers = [] 5310917Sbrandon.potter@amd.com 546911SBrad.Beckmann@amd.com # 556911SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 566911SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 576911SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 586911SBrad.Beckmann@amd.com # 596911SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 606911SBrad.Beckmann@amd.com l2_cntrl_nodes = [] 616911SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 626911SBrad.Beckmann@amd.com 636911SBrad.Beckmann@amd.com # 646911SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 656911SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 666911SBrad.Beckmann@amd.com # 678180SBrad.Beckmann@amd.com l2_bits = int(math.log(options.num_l2caches, 2)) 688180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 698257SBrad.Beckmann@amd.com 706911SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 716911SBrad.Beckmann@amd.com # 726911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 736911SBrad.Beckmann@amd.com # 746911SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 758180SBrad.Beckmann@amd.com assoc = options.l1i_assoc, 769319Smalek.musleh@gmail.com start_index_bit = block_size_bits, 779319Smalek.musleh@gmail.com is_icache = True) 786911SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 798180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 809319Smalek.musleh@gmail.com start_index_bit = block_size_bits, 819319Smalek.musleh@gmail.com is_icache = False) 826911SBrad.Beckmann@amd.com 8311266SBrad.Beckmann@amd.com # the ruby random tester reuses num_cpus to specify the 8411266SBrad.Beckmann@amd.com # number of cpu ports connected to the tester object, which 8511266SBrad.Beckmann@amd.com # is stored in system.cpu. because there is only ever one 8611266SBrad.Beckmann@amd.com # tester object, num_cpus is not necessarily equal to the 8711266SBrad.Beckmann@amd.com # size of system.cpu; therefore if len(system.cpu) == 1 8811266SBrad.Beckmann@amd.com # we use system.cpu[0] to set the clk_domain, thereby ensuring 8911266SBrad.Beckmann@amd.com # we don't index off the end of the cpu list. 9011266SBrad.Beckmann@amd.com if len(system.cpu) == 1: 9111266SBrad.Beckmann@amd.com clk_domain = system.cpu[0].clk_domain 9211266SBrad.Beckmann@amd.com else: 9311266SBrad.Beckmann@amd.com clk_domain = system.cpu[i].clk_domain 948322Ssteve.reinhardt@amd.com 9511266SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache, 9611266SBrad.Beckmann@amd.com L1Dcache=l1d_cache, 9711266SBrad.Beckmann@amd.com l2_select_num_bits=l2_bits, 9811266SBrad.Beckmann@amd.com send_evictions=send_evicts(options), 9911266SBrad.Beckmann@amd.com transitions_per_cycle=options.ports, 10011266SBrad.Beckmann@amd.com clk_domain=clk_domain, 10111266SBrad.Beckmann@amd.com ruby_system=ruby_system) 10211266SBrad.Beckmann@amd.com 10311266SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version=i, icache=l1i_cache, 10411266SBrad.Beckmann@amd.com dcache=l1d_cache, clk_domain=clk_domain, 10511266SBrad.Beckmann@amd.com ruby_system=ruby_system) 1066911SBrad.Beckmann@amd.com 1078322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 10810116Snilay@cs.wisc.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 1098322Ssteve.reinhardt@amd.com 1106911SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1116911SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1126911SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1136911SBrad.Beckmann@amd.com 11410311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 11511022Sjthestness@gmail.com l1_cntrl.mandatoryQueue = MessageBuffer() 11611022Sjthestness@gmail.com l1_cntrl.requestFromL1Cache = MessageBuffer() 11711022Sjthestness@gmail.com l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave 11811022Sjthestness@gmail.com l1_cntrl.responseFromL1Cache = MessageBuffer() 11911022Sjthestness@gmail.com l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave 12011022Sjthestness@gmail.com l1_cntrl.requestToL1Cache = MessageBuffer() 12111022Sjthestness@gmail.com l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 12211022Sjthestness@gmail.com l1_cntrl.responseToL1Cache = MessageBuffer() 12311022Sjthestness@gmail.com l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 12411022Sjthestness@gmail.com l1_cntrl.triggerQueue = MessageBuffer(ordered = True) 12510311Snilay@cs.wisc.edu 12610311Snilay@cs.wisc.edu 1278180SBrad.Beckmann@amd.com l2_index_start = block_size_bits + l2_bits 1288180SBrad.Beckmann@amd.com 1296911SBrad.Beckmann@amd.com for i in xrange(options.num_l2caches): 1306911SBrad.Beckmann@amd.com # 1316911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 1326911SBrad.Beckmann@amd.com # 1336911SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 1348180SBrad.Beckmann@amd.com assoc = options.l2_assoc, 1358180SBrad.Beckmann@amd.com start_index_bit = l2_index_start) 1366911SBrad.Beckmann@amd.com 1376911SBrad.Beckmann@amd.com l2_cntrl = L2Cache_Controller(version = i, 1389694Snilay@cs.wisc.edu L2cache = l2_cache, 1399841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1408436SBrad.Beckmann@amd.com ruby_system = ruby_system) 14110917Sbrandon.potter@amd.com 1429468Smalek.musleh@gmail.com exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1436911SBrad.Beckmann@amd.com l2_cntrl_nodes.append(l2_cntrl) 1448257SBrad.Beckmann@amd.com 14510311Snilay@cs.wisc.edu # Connect the L2 controllers and the network 14611022Sjthestness@gmail.com l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() 14711022Sjthestness@gmail.com l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave 14811022Sjthestness@gmail.com l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 14911022Sjthestness@gmail.com l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 15011022Sjthestness@gmail.com l2_cntrl.responseFromL2Cache = MessageBuffer() 15111022Sjthestness@gmail.com l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 15210311Snilay@cs.wisc.edu 15311022Sjthestness@gmail.com l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() 15411022Sjthestness@gmail.com l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master 15511022Sjthestness@gmail.com l2_cntrl.L1RequestToL2Cache = MessageBuffer() 15611022Sjthestness@gmail.com l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 15711022Sjthestness@gmail.com l2_cntrl.responseToL2Cache = MessageBuffer() 15811022Sjthestness@gmail.com l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 15911022Sjthestness@gmail.com l2_cntrl.triggerQueue = MessageBuffer(ordered = True) 16010311Snilay@cs.wisc.edu 1619793Sakash.bagdia@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 1629793Sakash.bagdia@arm.com # the ruby system. 1639793Sakash.bagdia@arm.com # clk_divider value is a fix to pass regression. 1649793Sakash.bagdia@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 1659793Sakash.bagdia@arm.com clk_domain=ruby_system.clk_domain, 1669793Sakash.bagdia@arm.com clk_divider=3) 1679793Sakash.bagdia@arm.com 1686911SBrad.Beckmann@amd.com 16912598Snikos.nikoleris@arm.com mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( 17012598Snikos.nikoleris@arm.com options, system.mem_ranges, bootmem, ruby_system, system) 17112598Snikos.nikoleris@arm.com dir_cntrl_nodes = mem_dir_cntrl_nodes[:] 17212598Snikos.nikoleris@arm.com if rom_dir_cntrl_node is not None: 17312598Snikos.nikoleris@arm.com dir_cntrl_nodes.append(rom_dir_cntrl_node) 17412065Snikos.nikoleris@arm.com for dir_cntrl in dir_cntrl_nodes: 17510311Snilay@cs.wisc.edu # Connect the directory controllers and the network 17611022Sjthestness@gmail.com dir_cntrl.requestToDir = MessageBuffer() 17711022Sjthestness@gmail.com dir_cntrl.requestToDir.slave = ruby_system.network.master 17811022Sjthestness@gmail.com dir_cntrl.responseToDir = MessageBuffer() 17911022Sjthestness@gmail.com dir_cntrl.responseToDir.slave = ruby_system.network.master 18011022Sjthestness@gmail.com dir_cntrl.responseFromDir = MessageBuffer() 18111022Sjthestness@gmail.com dir_cntrl.responseFromDir.master = ruby_system.network.slave 18211022Sjthestness@gmail.com dir_cntrl.forwardFromDir = MessageBuffer() 18311022Sjthestness@gmail.com dir_cntrl.forwardFromDir.master = ruby_system.network.slave 18411022Sjthestness@gmail.com dir_cntrl.responseFromMemory = MessageBuffer() 18510311Snilay@cs.wisc.edu 18610311Snilay@cs.wisc.edu 1878929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 1886911SBrad.Beckmann@amd.com # 1896911SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1906911SBrad.Beckmann@amd.com # 1916911SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 19210519Snilay@cs.wisc.edu ruby_system = ruby_system, 19310519Snilay@cs.wisc.edu slave = dma_port) 19410917Sbrandon.potter@amd.com 1956911SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1968477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 1979841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1988477Snilay@cs.wisc.edu ruby_system = ruby_system) 1996911SBrad.Beckmann@amd.com 2009468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 2016911SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 2028257SBrad.Beckmann@amd.com 20310519Snilay@cs.wisc.edu # Connect the dma controller to the network 20411022Sjthestness@gmail.com dma_cntrl.mandatoryQueue = MessageBuffer() 20511022Sjthestness@gmail.com dma_cntrl.responseFromDir = MessageBuffer() 20611022Sjthestness@gmail.com dma_cntrl.responseFromDir.slave = ruby_system.network.master 20711022Sjthestness@gmail.com dma_cntrl.reqToDir = MessageBuffer() 20811022Sjthestness@gmail.com dma_cntrl.reqToDir.master = ruby_system.network.slave 20911022Sjthestness@gmail.com dma_cntrl.respToDir = MessageBuffer() 21011022Sjthestness@gmail.com dma_cntrl.respToDir.master = ruby_system.network.slave 21111022Sjthestness@gmail.com dma_cntrl.triggerQueue = MessageBuffer(ordered = True) 21210519Snilay@cs.wisc.edu 21310311Snilay@cs.wisc.edu 2146911SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + \ 2156911SBrad.Beckmann@amd.com l2_cntrl_nodes + \ 2166911SBrad.Beckmann@amd.com dir_cntrl_nodes + \ 2176911SBrad.Beckmann@amd.com dma_cntrl_nodes 2186911SBrad.Beckmann@amd.com 21910519Snilay@cs.wisc.edu # Create the io controller and the sequencer 22010519Snilay@cs.wisc.edu if full_system: 22110519Snilay@cs.wisc.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 22210519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 22310519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 22410519Snilay@cs.wisc.edu dma_sequencer = io_seq, 22510519Snilay@cs.wisc.edu ruby_system = ruby_system) 22610519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 22710519Snilay@cs.wisc.edu 22810519Snilay@cs.wisc.edu # Connect the dma controller to the network 22911022Sjthestness@gmail.com io_controller.mandatoryQueue = MessageBuffer() 23011022Sjthestness@gmail.com io_controller.responseFromDir = MessageBuffer() 23111022Sjthestness@gmail.com io_controller.responseFromDir.slave = ruby_system.network.master 23211022Sjthestness@gmail.com io_controller.reqToDir = MessageBuffer() 23311022Sjthestness@gmail.com io_controller.reqToDir.master = ruby_system.network.slave 23411022Sjthestness@gmail.com io_controller.respToDir = MessageBuffer() 23511022Sjthestness@gmail.com io_controller.respToDir.master = ruby_system.network.slave 23611022Sjthestness@gmail.com io_controller.triggerQueue = MessageBuffer(ordered = True) 23710519Snilay@cs.wisc.edu 23810519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 23910519Snilay@cs.wisc.edu 24010519Snilay@cs.wisc.edu 24111065Snilay@cs.wisc.edu ruby_system.network.number_of_virtual_networks = 3 2429100SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 24312598Snikos.nikoleris@arm.com return (cpu_sequencers, mem_dir_cntrl_nodes, topology) 244