MOESI_CMP_directory.py revision 10524
16911SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26911SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36911SBrad.Beckmann@amd.com# All rights reserved. 46911SBrad.Beckmann@amd.com# 56911SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66911SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76911SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96911SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116911SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126911SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136911SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146911SBrad.Beckmann@amd.com# this software without specific prior written permission. 156911SBrad.Beckmann@amd.com# 166911SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176911SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186911SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196911SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206911SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216911SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226911SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236911SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246911SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256911SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266911SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276911SBrad.Beckmann@amd.com# 286911SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296911SBrad.Beckmann@amd.com 306911SBrad.Beckmann@amd.comimport math 316911SBrad.Beckmann@amd.comimport m5 326911SBrad.Beckmann@amd.comfrom m5.objects import * 336911SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 349100SBrad.Beckmann@amd.comfrom Ruby import create_topology 356911SBrad.Beckmann@amd.com 366911SBrad.Beckmann@amd.com# 376911SBrad.Beckmann@amd.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 386911SBrad.Beckmann@amd.com# 396911SBrad.Beckmann@amd.comclass L1Cache(RubyCache): 406911SBrad.Beckmann@amd.com latency = 3 416911SBrad.Beckmann@amd.com 426911SBrad.Beckmann@amd.com# 436911SBrad.Beckmann@amd.com# Note: the L2 Cache latency is not currently used 446911SBrad.Beckmann@amd.com# 456911SBrad.Beckmann@amd.comclass L2Cache(RubyCache): 466911SBrad.Beckmann@amd.com latency = 15 476911SBrad.Beckmann@amd.com 487538SBrad.Beckmann@amd.comdef define_options(parser): 497538SBrad.Beckmann@amd.com return 507538SBrad.Beckmann@amd.com 5110519Snilay@cs.wisc.edudef create_system(options, full_system, system, dma_ports, ruby_system): 528436SBrad.Beckmann@amd.com 536911SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': 546911SBrad.Beckmann@amd.com panic("This script requires the MOESI_CMP_directory protocol to be built.") 556911SBrad.Beckmann@amd.com 566911SBrad.Beckmann@amd.com cpu_sequencers = [] 576911SBrad.Beckmann@amd.com 586911SBrad.Beckmann@amd.com # 596911SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 606911SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 616911SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 626911SBrad.Beckmann@amd.com # 636911SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 646911SBrad.Beckmann@amd.com l2_cntrl_nodes = [] 656911SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 666911SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 676911SBrad.Beckmann@amd.com 686911SBrad.Beckmann@amd.com # 696911SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 706911SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 716911SBrad.Beckmann@amd.com # 728180SBrad.Beckmann@amd.com l2_bits = int(math.log(options.num_l2caches, 2)) 738180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 748257SBrad.Beckmann@amd.com 756911SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 766911SBrad.Beckmann@amd.com # 776911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 786911SBrad.Beckmann@amd.com # 796911SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 808180SBrad.Beckmann@amd.com assoc = options.l1i_assoc, 819319Smalek.musleh@gmail.com start_index_bit = block_size_bits, 829319Smalek.musleh@gmail.com is_icache = True) 836911SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 848180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 859319Smalek.musleh@gmail.com start_index_bit = block_size_bits, 869319Smalek.musleh@gmail.com is_icache = False) 876911SBrad.Beckmann@amd.com 888322Ssteve.reinhardt@amd.com l1_cntrl = L1Cache_Controller(version = i, 899694Snilay@cs.wisc.edu L1Icache = l1i_cache, 909694Snilay@cs.wisc.edu L1Dcache = l1d_cache, 918436SBrad.Beckmann@amd.com l2_select_num_bits = l2_bits, 928717Snilay@cs.wisc.edu send_evictions = ( 938717Snilay@cs.wisc.edu options.cpu_type == "detailed"), 949841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 9510300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 968436SBrad.Beckmann@amd.com ruby_system = ruby_system) 978322Ssteve.reinhardt@amd.com 987015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 997015SBrad.Beckmann@amd.com icache = l1i_cache, 1006911SBrad.Beckmann@amd.com dcache = l1d_cache, 10110300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 1028436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1036911SBrad.Beckmann@amd.com 1048322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 10510116Snilay@cs.wisc.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 1068322Ssteve.reinhardt@amd.com 1076911SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1086911SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1096911SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1106911SBrad.Beckmann@amd.com 11110311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 11210311Snilay@cs.wisc.edu l1_cntrl.requestFromL1Cache = ruby_system.network.slave 11310311Snilay@cs.wisc.edu l1_cntrl.responseFromL1Cache = ruby_system.network.slave 11410311Snilay@cs.wisc.edu l1_cntrl.requestToL1Cache = ruby_system.network.master 11510311Snilay@cs.wisc.edu l1_cntrl.responseToL1Cache = ruby_system.network.master 11610311Snilay@cs.wisc.edu 11710311Snilay@cs.wisc.edu 1188180SBrad.Beckmann@amd.com l2_index_start = block_size_bits + l2_bits 1198180SBrad.Beckmann@amd.com 1206911SBrad.Beckmann@amd.com for i in xrange(options.num_l2caches): 1216911SBrad.Beckmann@amd.com # 1226911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 1236911SBrad.Beckmann@amd.com # 1246911SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 1258180SBrad.Beckmann@amd.com assoc = options.l2_assoc, 1268180SBrad.Beckmann@amd.com start_index_bit = l2_index_start) 1276911SBrad.Beckmann@amd.com 1286911SBrad.Beckmann@amd.com l2_cntrl = L2Cache_Controller(version = i, 1299694Snilay@cs.wisc.edu L2cache = l2_cache, 1309841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1318436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1326911SBrad.Beckmann@amd.com 1339468Smalek.musleh@gmail.com exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1346911SBrad.Beckmann@amd.com l2_cntrl_nodes.append(l2_cntrl) 1358257SBrad.Beckmann@amd.com 13610311Snilay@cs.wisc.edu # Connect the L2 controllers and the network 13710311Snilay@cs.wisc.edu l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave 13810311Snilay@cs.wisc.edu l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 13910311Snilay@cs.wisc.edu l2_cntrl.responseFromL2Cache = ruby_system.network.slave 14010311Snilay@cs.wisc.edu 14110311Snilay@cs.wisc.edu l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master 14210311Snilay@cs.wisc.edu l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 14310311Snilay@cs.wisc.edu l2_cntrl.responseToL2Cache = ruby_system.network.master 14410311Snilay@cs.wisc.edu 14510311Snilay@cs.wisc.edu 1469826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1479798Snilay@cs.wisc.edu assert(phys_mem_size % options.num_dirs == 0) 1486911SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1496911SBrad.Beckmann@amd.com 15010311Snilay@cs.wisc.edu 1519793Sakash.bagdia@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 1529793Sakash.bagdia@arm.com # the ruby system. 1539793Sakash.bagdia@arm.com # clk_divider value is a fix to pass regression. 1549793Sakash.bagdia@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 1559793Sakash.bagdia@arm.com clk_domain=ruby_system.clk_domain, 1569793Sakash.bagdia@arm.com clk_divider=3) 1579793Sakash.bagdia@arm.com 1586911SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1596911SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1606911SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1616911SBrad.Beckmann@amd.com 1626911SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 16310524Snilay@cs.wisc.edu directory = RubyDirectoryMemory( 16410524Snilay@cs.wisc.edu version = i, size = dir_size), 1659841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1668436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1676911SBrad.Beckmann@amd.com 1689468Smalek.musleh@gmail.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1696911SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1706911SBrad.Beckmann@amd.com 17110311Snilay@cs.wisc.edu # Connect the directory controllers and the network 17210311Snilay@cs.wisc.edu dir_cntrl.requestToDir = ruby_system.network.master 17310311Snilay@cs.wisc.edu dir_cntrl.responseToDir = ruby_system.network.master 17410311Snilay@cs.wisc.edu dir_cntrl.responseFromDir = ruby_system.network.slave 17510311Snilay@cs.wisc.edu dir_cntrl.forwardFromDir = ruby_system.network.slave 17610311Snilay@cs.wisc.edu 17710311Snilay@cs.wisc.edu 1788929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 1796911SBrad.Beckmann@amd.com # 1806911SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1816911SBrad.Beckmann@amd.com # 1826911SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 18310519Snilay@cs.wisc.edu ruby_system = ruby_system, 18410519Snilay@cs.wisc.edu slave = dma_port) 1856911SBrad.Beckmann@amd.com 1866911SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1878477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 1889841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1898477Snilay@cs.wisc.edu ruby_system = ruby_system) 1906911SBrad.Beckmann@amd.com 1919468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 1926911SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1938257SBrad.Beckmann@amd.com 19410519Snilay@cs.wisc.edu # Connect the dma controller to the network 19510519Snilay@cs.wisc.edu dma_cntrl.responseFromDir = ruby_system.network.master 19610519Snilay@cs.wisc.edu dma_cntrl.reqToDir = ruby_system.network.slave 19710519Snilay@cs.wisc.edu dma_cntrl.respToDir = ruby_system.network.slave 19810519Snilay@cs.wisc.edu 19910311Snilay@cs.wisc.edu 2006911SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + \ 2016911SBrad.Beckmann@amd.com l2_cntrl_nodes + \ 2026911SBrad.Beckmann@amd.com dir_cntrl_nodes + \ 2036911SBrad.Beckmann@amd.com dma_cntrl_nodes 2046911SBrad.Beckmann@amd.com 20510519Snilay@cs.wisc.edu # Create the io controller and the sequencer 20610519Snilay@cs.wisc.edu if full_system: 20710519Snilay@cs.wisc.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 20810519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 20910519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 21010519Snilay@cs.wisc.edu dma_sequencer = io_seq, 21110519Snilay@cs.wisc.edu ruby_system = ruby_system) 21210519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 21310519Snilay@cs.wisc.edu 21410519Snilay@cs.wisc.edu # Connect the dma controller to the network 21510519Snilay@cs.wisc.edu io_controller.responseFromDir = ruby_system.network.master 21610519Snilay@cs.wisc.edu io_controller.reqToDir = ruby_system.network.slave 21710519Snilay@cs.wisc.edu io_controller.respToDir = ruby_system.network.slave 21810519Snilay@cs.wisc.edu 21910519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 22010519Snilay@cs.wisc.edu 22110519Snilay@cs.wisc.edu 2229100SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 2239100SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, topology) 224