MOESI_CMP_directory.py revision 10300
16911SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26911SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36911SBrad.Beckmann@amd.com# All rights reserved. 46911SBrad.Beckmann@amd.com# 56911SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66911SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76911SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96911SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116911SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126911SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136911SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146911SBrad.Beckmann@amd.com# this software without specific prior written permission. 156911SBrad.Beckmann@amd.com# 166911SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176911SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186911SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196911SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206911SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216911SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226911SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236911SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246911SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256911SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266911SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276911SBrad.Beckmann@amd.com# 286911SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296911SBrad.Beckmann@amd.com 306911SBrad.Beckmann@amd.comimport math 316911SBrad.Beckmann@amd.comimport m5 326911SBrad.Beckmann@amd.comfrom m5.objects import * 336911SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 349100SBrad.Beckmann@amd.comfrom Ruby import create_topology 356911SBrad.Beckmann@amd.com 366911SBrad.Beckmann@amd.com# 376911SBrad.Beckmann@amd.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 386911SBrad.Beckmann@amd.com# 396911SBrad.Beckmann@amd.comclass L1Cache(RubyCache): 406911SBrad.Beckmann@amd.com latency = 3 416911SBrad.Beckmann@amd.com 426911SBrad.Beckmann@amd.com# 436911SBrad.Beckmann@amd.com# Note: the L2 Cache latency is not currently used 446911SBrad.Beckmann@amd.com# 456911SBrad.Beckmann@amd.comclass L2Cache(RubyCache): 466911SBrad.Beckmann@amd.com latency = 15 476911SBrad.Beckmann@amd.com 487538SBrad.Beckmann@amd.comdef define_options(parser): 497538SBrad.Beckmann@amd.com return 507538SBrad.Beckmann@amd.com 5110116Snilay@cs.wisc.edudef create_system(options, system, dma_ports, ruby_system): 528436SBrad.Beckmann@amd.com 536911SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': 546911SBrad.Beckmann@amd.com panic("This script requires the MOESI_CMP_directory protocol to be built.") 556911SBrad.Beckmann@amd.com 566911SBrad.Beckmann@amd.com cpu_sequencers = [] 576911SBrad.Beckmann@amd.com 586911SBrad.Beckmann@amd.com # 596911SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 606911SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 616911SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 626911SBrad.Beckmann@amd.com # 636911SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 646911SBrad.Beckmann@amd.com l2_cntrl_nodes = [] 656911SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 666911SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 676911SBrad.Beckmann@amd.com 686911SBrad.Beckmann@amd.com # 696911SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 706911SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 716911SBrad.Beckmann@amd.com # 728180SBrad.Beckmann@amd.com l2_bits = int(math.log(options.num_l2caches, 2)) 738180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 748257SBrad.Beckmann@amd.com 756911SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 766911SBrad.Beckmann@amd.com # 776911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 786911SBrad.Beckmann@amd.com # 796911SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 808180SBrad.Beckmann@amd.com assoc = options.l1i_assoc, 819319Smalek.musleh@gmail.com start_index_bit = block_size_bits, 829319Smalek.musleh@gmail.com is_icache = True) 836911SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 848180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 859319Smalek.musleh@gmail.com start_index_bit = block_size_bits, 869319Smalek.musleh@gmail.com is_icache = False) 876911SBrad.Beckmann@amd.com 888322Ssteve.reinhardt@amd.com l1_cntrl = L1Cache_Controller(version = i, 899694Snilay@cs.wisc.edu L1Icache = l1i_cache, 909694Snilay@cs.wisc.edu L1Dcache = l1d_cache, 918436SBrad.Beckmann@amd.com l2_select_num_bits = l2_bits, 928717Snilay@cs.wisc.edu send_evictions = ( 938717Snilay@cs.wisc.edu options.cpu_type == "detailed"), 949841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 9510300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 968436SBrad.Beckmann@amd.com ruby_system = ruby_system) 978322Ssteve.reinhardt@amd.com 987015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 997015SBrad.Beckmann@amd.com icache = l1i_cache, 1006911SBrad.Beckmann@amd.com dcache = l1d_cache, 10110300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 1028436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1036911SBrad.Beckmann@amd.com 1048322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 10510116Snilay@cs.wisc.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 1068322Ssteve.reinhardt@amd.com 1076911SBrad.Beckmann@amd.com # 1086911SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1096911SBrad.Beckmann@amd.com # 1106911SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1116911SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1126911SBrad.Beckmann@amd.com 1138180SBrad.Beckmann@amd.com l2_index_start = block_size_bits + l2_bits 1148180SBrad.Beckmann@amd.com 1156911SBrad.Beckmann@amd.com for i in xrange(options.num_l2caches): 1166911SBrad.Beckmann@amd.com # 1176911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 1186911SBrad.Beckmann@amd.com # 1196911SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 1208180SBrad.Beckmann@amd.com assoc = options.l2_assoc, 1218180SBrad.Beckmann@amd.com start_index_bit = l2_index_start) 1226911SBrad.Beckmann@amd.com 1236911SBrad.Beckmann@amd.com l2_cntrl = L2Cache_Controller(version = i, 1249694Snilay@cs.wisc.edu L2cache = l2_cache, 1259841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1268436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1276911SBrad.Beckmann@amd.com 1289468Smalek.musleh@gmail.com exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1296911SBrad.Beckmann@amd.com l2_cntrl_nodes.append(l2_cntrl) 1308257SBrad.Beckmann@amd.com 1319826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1329798Snilay@cs.wisc.edu assert(phys_mem_size % options.num_dirs == 0) 1336911SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1346911SBrad.Beckmann@amd.com 1359793Sakash.bagdia@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 1369793Sakash.bagdia@arm.com # the ruby system. 1379793Sakash.bagdia@arm.com # clk_divider value is a fix to pass regression. 1389793Sakash.bagdia@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 1399793Sakash.bagdia@arm.com clk_domain=ruby_system.clk_domain, 1409793Sakash.bagdia@arm.com clk_divider=3) 1419793Sakash.bagdia@arm.com 1426911SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1436911SBrad.Beckmann@amd.com # 1446911SBrad.Beckmann@amd.com # Create the Ruby objects associated with the directory controller 1456911SBrad.Beckmann@amd.com # 1466911SBrad.Beckmann@amd.com 1479793Sakash.bagdia@arm.com mem_cntrl = RubyMemoryControl( 1489793Sakash.bagdia@arm.com clk_domain = ruby_system.memctrl_clk_domain, 1499793Sakash.bagdia@arm.com version = i, 1509793Sakash.bagdia@arm.com ruby_system = ruby_system) 1516911SBrad.Beckmann@amd.com 1526911SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1536911SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1546911SBrad.Beckmann@amd.com 1556911SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1566911SBrad.Beckmann@amd.com directory = \ 1576911SBrad.Beckmann@amd.com RubyDirectoryMemory(version = i, 1589693Snilay@cs.wisc.edu size = dir_size, 1599693Snilay@cs.wisc.edu use_map = options.use_map), 1608436SBrad.Beckmann@amd.com memBuffer = mem_cntrl, 1619841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1628436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1636911SBrad.Beckmann@amd.com 1649468Smalek.musleh@gmail.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1656911SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1666911SBrad.Beckmann@amd.com 1678929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 1686911SBrad.Beckmann@amd.com # 1696911SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1706911SBrad.Beckmann@amd.com # 1716911SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1728477Snilay@cs.wisc.edu ruby_system = ruby_system) 1736911SBrad.Beckmann@amd.com 1746911SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1758477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 1769841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1778477Snilay@cs.wisc.edu ruby_system = ruby_system) 1786911SBrad.Beckmann@amd.com 1799468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 1809468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 1816911SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1828257SBrad.Beckmann@amd.com 1836911SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + \ 1846911SBrad.Beckmann@amd.com l2_cntrl_nodes + \ 1856911SBrad.Beckmann@amd.com dir_cntrl_nodes + \ 1866911SBrad.Beckmann@amd.com dma_cntrl_nodes 1876911SBrad.Beckmann@amd.com 1889100SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 1899100SBrad.Beckmann@amd.com 1909100SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, topology) 191