MI_example.py revision 9841:69c158420c51 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the cache latency is only used by the sequencer on fast path hits
38#
39class Cache(RubyCache):
40    latency = 3
41
42def define_options(parser):
43    return
44
45def create_system(options, system, piobus, dma_ports, ruby_system):
46
47    if buildEnv['PROTOCOL'] != 'MI_example':
48        panic("This script requires the MI_example protocol to be built.")
49
50    cpu_sequencers = []
51
52    #
53    # The ruby network creation expects the list of nodes in the system to be
54    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
55    # listed before the directory nodes and directory nodes before dma nodes, etc.
56    #
57    l1_cntrl_nodes = []
58    dir_cntrl_nodes = []
59    dma_cntrl_nodes = []
60
61    #
62    # Must create the individual controllers before the network to ensure the
63    # controller constructors are called before the network constructor
64    #
65    block_size_bits = int(math.log(options.cacheline_size, 2))
66
67    cntrl_count = 0
68
69    for i in xrange(options.num_cpus):
70        #
71        # First create the Ruby objects associated with this cpu
72        # Only one cache exists for this protocol, so by default use the L1D
73        # config parameters.
74        #
75        cache = Cache(size = options.l1d_size,
76                      assoc = options.l1d_assoc,
77                      start_index_bit = block_size_bits)
78
79        #
80        # Only one unified L1 cache exists.  Can cache instructions and data.
81        #
82        l1_cntrl = L1Cache_Controller(version = i,
83                                      cntrl_id = cntrl_count,
84                                      cacheMemory = cache,
85                                      send_evictions = (
86                                          options.cpu_type == "detailed"),
87                                      transitions_per_cycle = options.ports,
88                                      ruby_system = ruby_system)
89
90        cpu_seq = RubySequencer(version = i,
91                                icache = cache,
92                                dcache = cache,
93                                ruby_system = ruby_system)
94
95        l1_cntrl.sequencer = cpu_seq
96
97        if piobus != None:
98            cpu_seq.pio_port = piobus.slave
99
100        exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
101        #
102        # Add controllers and sequencers to the appropriate lists
103        #
104        cpu_sequencers.append(cpu_seq)
105        l1_cntrl_nodes.append(l1_cntrl)
106
107        cntrl_count += 1
108
109    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
110    assert(phys_mem_size % options.num_dirs == 0)
111    mem_module_size = phys_mem_size / options.num_dirs
112
113    # Run each of the ruby memory controllers at a ratio of the frequency of
114    # the ruby system.
115    # clk_divider value is a fix to pass regression.
116    ruby_system.memctrl_clk_domain = DerivedClockDomain(
117                                          clk_domain=ruby_system.clk_domain,
118                                          clk_divider=3)
119
120    for i in xrange(options.num_dirs):
121        #
122        # Create the Ruby objects associated with the directory controller
123        #
124
125        mem_cntrl = RubyMemoryControl(
126                              clk_domain = ruby_system.memctrl_clk_domain,
127                              version = i,
128                              ruby_system = ruby_system)
129
130        dir_size = MemorySize('0B')
131        dir_size.value = mem_module_size
132
133        dir_cntrl = Directory_Controller(version = i,
134                                         cntrl_id = cntrl_count,
135                                         directory = \
136                                         RubyDirectoryMemory( \
137                                                    version = i,
138                                                    size = dir_size,
139                                                    use_map = options.use_map,
140                                                    map_levels = \
141                                                      options.map_levels),
142                                         memBuffer = mem_cntrl,
143                                         transitions_per_cycle = options.ports,
144                                         ruby_system = ruby_system)
145
146        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
147        dir_cntrl_nodes.append(dir_cntrl)
148
149        cntrl_count += 1
150
151    for i, dma_port in enumerate(dma_ports):
152        #
153        # Create the Ruby objects associated with the dma controller
154        #
155        dma_seq = DMASequencer(version = i,
156                               ruby_system = ruby_system)
157
158        dma_cntrl = DMA_Controller(version = i,
159                                   cntrl_id = cntrl_count,
160                                   dma_sequencer = dma_seq,
161                                   transitions_per_cycle = options.ports,
162                                   ruby_system = ruby_system)
163
164        exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
165        exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
166        dma_cntrl_nodes.append(dma_cntrl)
167        cntrl_count += 1
168
169    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
170
171    topology = create_topology(all_cntrls, options)
172
173    return (cpu_sequencers, dir_cntrl_nodes, topology)
174