MI_example.py revision 9798:52679402e09c
14120Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 24120Sgblack@eecs.umich.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 37087Snate@binkert.org# All rights reserved. 47087Snate@binkert.org# 57087Snate@binkert.org# Redistribution and use in source and binary forms, with or without 67087Snate@binkert.org# modification, are permitted provided that the following conditions are 77087Snate@binkert.org# met: redistributions of source code must retain the above copyright 87087Snate@binkert.org# notice, this list of conditions and the following disclaimer; 97087Snate@binkert.org# redistributions in binary form must reproduce the above copyright 107087Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 117087Snate@binkert.org# documentation and/or other materials provided with the distribution; 127087Snate@binkert.org# neither the name of the copyright holders nor the names of its 137087Snate@binkert.org# contributors may be used to endorse or promote products derived from 147087Snate@binkert.org# this software without specific prior written permission. 154120Sgblack@eecs.umich.edu# 164120Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174120Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184120Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194120Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204120Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214120Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224120Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234120Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244120Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254120Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264120Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274120Sgblack@eecs.umich.edu# 284120Sgblack@eecs.umich.edu# Authors: Brad Beckmann 294120Sgblack@eecs.umich.edu 304120Sgblack@eecs.umich.eduimport math 314120Sgblack@eecs.umich.eduimport m5 324120Sgblack@eecs.umich.edufrom m5.objects import * 334120Sgblack@eecs.umich.edufrom m5.defines import buildEnv 344120Sgblack@eecs.umich.edufrom Ruby import create_topology 354120Sgblack@eecs.umich.edu 364120Sgblack@eecs.umich.edu# 374120Sgblack@eecs.umich.edu# Note: the cache latency is only used by the sequencer on fast path hits 384120Sgblack@eecs.umich.edu# 394120Sgblack@eecs.umich.educlass Cache(RubyCache): 404120Sgblack@eecs.umich.edu latency = 3 414120Sgblack@eecs.umich.edu 424120Sgblack@eecs.umich.edudef define_options(parser): 434202Sbinkertn@umich.edu return 445069Sgblack@eecs.umich.edu 454202Sbinkertn@umich.edudef create_system(options, system, piobus, dma_ports, ruby_system): 465659Sgblack@eecs.umich.edu 474601Sgblack@eecs.umich.edu if buildEnv['PROTOCOL'] != 'MI_example': 485124Sgblack@eecs.umich.edu panic("This script requires the MI_example protocol to be built.") 497966Sgblack@eecs.umich.edu 505083Sgblack@eecs.umich.edu cpu_sequencers = [] 514679Sgblack@eecs.umich.edu 526515Sgblack@eecs.umich.edu # 535083Sgblack@eecs.umich.edu # The ruby network creation expects the list of nodes in the system to be 544679Sgblack@eecs.umich.edu # consistent with the NetDest list. Therefore the l1 controller nodes must be 554679Sgblack@eecs.umich.edu # listed before the directory nodes and directory nodes before dma nodes, etc. 568745Sgblack@eecs.umich.edu # 576313Sgblack@eecs.umich.edu l1_cntrl_nodes = [] 586365Sgblack@eecs.umich.edu dir_cntrl_nodes = [] 595124Sgblack@eecs.umich.edu dma_cntrl_nodes = [] 608752Sgblack@eecs.umich.edu 614249Sgblack@eecs.umich.edu # 624240Sgblack@eecs.umich.edu # Must create the individual controllers before the network to ensure the 634202Sbinkertn@umich.edu # controller constructors are called before the network constructor 644997Sgblack@eecs.umich.edu # 657624Sgblack@eecs.umich.edu block_size_bits = int(math.log(options.cacheline_size, 2)) 665135Sgblack@eecs.umich.edu 678753Sgblack@eecs.umich.edu cntrl_count = 0 684997Sgblack@eecs.umich.edu 698745Sgblack@eecs.umich.edu for i in xrange(options.num_cpus): 706365Sgblack@eecs.umich.edu # 718740Sgblack@eecs.umich.edu # First create the Ruby objects associated with this cpu 726365Sgblack@eecs.umich.edu # Only one cache exists for this protocol, so by default use the L1D 738740Sgblack@eecs.umich.edu # config parameters. 748745Sgblack@eecs.umich.edu # 758752Sgblack@eecs.umich.edu cache = Cache(size = options.l1d_size, 768752Sgblack@eecs.umich.edu assoc = options.l1d_assoc, 778335Snate@binkert.org start_index_bit = block_size_bits) 788335Snate@binkert.org 794120Sgblack@eecs.umich.edu # 804202Sbinkertn@umich.edu # Only one unified L1 cache exists. Can cache instructions and data. 815649Sgblack@eecs.umich.edu # 825132Sgblack@eecs.umich.edu l1_cntrl = L1Cache_Controller(version = i, 835132Sgblack@eecs.umich.edu cntrl_id = cntrl_count, 844202Sbinkertn@umich.edu cacheMemory = cache, 855299Sgblack@eecs.umich.edu send_evictions = ( 865132Sgblack@eecs.umich.edu options.cpu_type == "detailed"), 875086Sgblack@eecs.umich.edu ruby_system = ruby_system) 884202Sbinkertn@umich.edu 894202Sbinkertn@umich.edu cpu_seq = RubySequencer(version = i, 904120Sgblack@eecs.umich.edu icache = cache, 914202Sbinkertn@umich.edu dcache = cache, 924202Sbinkertn@umich.edu ruby_system = ruby_system) 934202Sbinkertn@umich.edu 944120Sgblack@eecs.umich.edu l1_cntrl.sequencer = cpu_seq 955069Sgblack@eecs.umich.edu 965081Sgblack@eecs.umich.edu if piobus != None: 975081Sgblack@eecs.umich.edu cpu_seq.pio_port = piobus.slave 985081Sgblack@eecs.umich.edu 995081Sgblack@eecs.umich.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 1005081Sgblack@eecs.umich.edu # 1015081Sgblack@eecs.umich.edu # Add controllers and sequencers to the appropriate lists 1025081Sgblack@eecs.umich.edu # 1035081Sgblack@eecs.umich.edu cpu_sequencers.append(cpu_seq) 1045081Sgblack@eecs.umich.edu l1_cntrl_nodes.append(l1_cntrl) 1055081Sgblack@eecs.umich.edu 1065081Sgblack@eecs.umich.edu cntrl_count += 1 1075081Sgblack@eecs.umich.edu 1085081Sgblack@eecs.umich.edu phys_mem_size = sum(map(lambda mem: mem.range.size(), 1095081Sgblack@eecs.umich.edu system.memories.unproxy(system))) 1105081Sgblack@eecs.umich.edu assert(phys_mem_size % options.num_dirs == 0) 1115081Sgblack@eecs.umich.edu mem_module_size = phys_mem_size / options.num_dirs 1125081Sgblack@eecs.umich.edu 1135081Sgblack@eecs.umich.edu # Run each of the ruby memory controllers at a ratio of the frequency of 1145081Sgblack@eecs.umich.edu # the ruby system. 1155081Sgblack@eecs.umich.edu # clk_divider value is a fix to pass regression. 1165081Sgblack@eecs.umich.edu ruby_system.memctrl_clk_domain = DerivedClockDomain( 1175081Sgblack@eecs.umich.edu clk_domain=ruby_system.clk_domain, 1185081Sgblack@eecs.umich.edu clk_divider=3) 1195081Sgblack@eecs.umich.edu 1205081Sgblack@eecs.umich.edu for i in xrange(options.num_dirs): 1215081Sgblack@eecs.umich.edu # 1225081Sgblack@eecs.umich.edu # Create the Ruby objects associated with the directory controller 1235081Sgblack@eecs.umich.edu # 1245081Sgblack@eecs.umich.edu 1255081Sgblack@eecs.umich.edu mem_cntrl = RubyMemoryControl( 1265081Sgblack@eecs.umich.edu clk_domain = ruby_system.memctrl_clk_domain, 1275081Sgblack@eecs.umich.edu version = i, 1285081Sgblack@eecs.umich.edu ruby_system = ruby_system) 1295081Sgblack@eecs.umich.edu 1305081Sgblack@eecs.umich.edu dir_size = MemorySize('0B') 1315081Sgblack@eecs.umich.edu dir_size.value = mem_module_size 1325081Sgblack@eecs.umich.edu 1335081Sgblack@eecs.umich.edu dir_cntrl = Directory_Controller(version = i, 1345081Sgblack@eecs.umich.edu cntrl_id = cntrl_count, 1355081Sgblack@eecs.umich.edu directory = \ 1365081Sgblack@eecs.umich.edu RubyDirectoryMemory( \ 1375081Sgblack@eecs.umich.edu version = i, 1385081Sgblack@eecs.umich.edu size = dir_size, 1395081Sgblack@eecs.umich.edu use_map = options.use_map, 1405081Sgblack@eecs.umich.edu map_levels = \ 1415081Sgblack@eecs.umich.edu options.map_levels), 1425081Sgblack@eecs.umich.edu memBuffer = mem_cntrl, 1435081Sgblack@eecs.umich.edu ruby_system = ruby_system) 1445081Sgblack@eecs.umich.edu 1455081Sgblack@eecs.umich.edu exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1465081Sgblack@eecs.umich.edu dir_cntrl_nodes.append(dir_cntrl) 1475081Sgblack@eecs.umich.edu 1485081Sgblack@eecs.umich.edu cntrl_count += 1 1495081Sgblack@eecs.umich.edu 1505081Sgblack@eecs.umich.edu for i, dma_port in enumerate(dma_ports): 1515680Sgblack@eecs.umich.edu # 1525081Sgblack@eecs.umich.edu # Create the Ruby objects associated with the dma controller 1535933Sgblack@eecs.umich.edu # 1545173Sgblack@eecs.umich.edu dma_seq = DMASequencer(version = i, 1555359Sgblack@eecs.umich.edu ruby_system = ruby_system) 1565081Sgblack@eecs.umich.edu 1575149Sgblack@eecs.umich.edu dma_cntrl = DMA_Controller(version = i, 1585298Sgblack@eecs.umich.edu cntrl_id = cntrl_count, 1595081Sgblack@eecs.umich.edu dma_sequencer = dma_seq, 1605081Sgblack@eecs.umich.edu ruby_system = ruby_system) 1615081Sgblack@eecs.umich.edu 1625081Sgblack@eecs.umich.edu exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 1635081Sgblack@eecs.umich.edu exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 1645081Sgblack@eecs.umich.edu dma_cntrl_nodes.append(dma_cntrl) 1655081Sgblack@eecs.umich.edu cntrl_count += 1 1665081Sgblack@eecs.umich.edu 1675081Sgblack@eecs.umich.edu all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 1685081Sgblack@eecs.umich.edu 1695081Sgblack@eecs.umich.edu topology = create_topology(all_cntrls, options) 1705081Sgblack@eecs.umich.edu 1715081Sgblack@eecs.umich.edu return (cpu_sequencers, dir_cntrl_nodes, topology) 1725081Sgblack@eecs.umich.edu