MI_example.py revision 8436:5648986156db 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the cache latency is only used by the sequencer on fast path hits
37#
38class Cache(RubyCache):
39    latency = 3
40
41def define_options(parser):
42    return
43
44def create_system(options, system, piobus, dma_devices, ruby_system):
45
46    if buildEnv['PROTOCOL'] != 'MI_example':
47        panic("This script requires the MI_example protocol to be built.")
48
49    cpu_sequencers = []
50
51    #
52    # The ruby network creation expects the list of nodes in the system to be
53    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
54    # listed before the directory nodes and directory nodes before dma nodes, etc.
55    #
56    l1_cntrl_nodes = []
57    dir_cntrl_nodes = []
58    dma_cntrl_nodes = []
59
60    #
61    # Must create the individual controllers before the network to ensure the
62    # controller constructors are called before the network constructor
63    #
64    block_size_bits = int(math.log(options.cacheline_size, 2))
65
66    cntrl_count = 0
67
68    for i in xrange(options.num_cpus):
69        #
70        # First create the Ruby objects associated with this cpu
71        # Only one cache exists for this protocol, so by default use the L1D
72        # config parameters.
73        #
74        cache = Cache(size = options.l1d_size,
75                      assoc = options.l1d_assoc,
76                      start_index_bit = block_size_bits)
77
78        #
79        # Only one unified L1 cache exists.  Can cache instructions and data.
80        #
81        l1_cntrl = L1Cache_Controller(version = i,
82                                      cntrl_id = cntrl_count,
83                                      cacheMemory = cache,
84                                      ruby_system = ruby_system)
85
86        cpu_seq = RubySequencer(version = i,
87                                icache = cache,
88                                dcache = cache,
89                                physMemPort = system.physmem.port,
90                                physmem = system.physmem,
91                                ruby_system = ruby_system)
92
93        l1_cntrl.sequencer = cpu_seq
94
95        if piobus != None:
96            cpu_seq.pio_port = piobus.port
97
98        exec("system.l1_cntrl%d = l1_cntrl" % i)
99        #
100        # Add controllers and sequencers to the appropriate lists
101        #
102        cpu_sequencers.append(cpu_seq)
103        l1_cntrl_nodes.append(l1_cntrl)
104
105        cntrl_count += 1
106
107    phys_mem_size = long(system.physmem.range.second) - \
108                      long(system.physmem.range.first) + 1
109    mem_module_size = phys_mem_size / options.num_dirs
110
111    for i in xrange(options.num_dirs):
112        #
113        # Create the Ruby objects associated with the directory controller
114        #
115
116        mem_cntrl = RubyMemoryControl(version = i)
117
118        dir_size = MemorySize('0B')
119        dir_size.value = mem_module_size
120
121        dir_cntrl = Directory_Controller(version = i,
122                                         cntrl_id = cntrl_count,
123                                         directory = \
124                                         RubyDirectoryMemory( \
125                                                    version = i,
126                                                    size = dir_size,
127                                                    use_map = options.use_map,
128                                                    map_levels = \
129                                                      options.map_levels),
130                                         memBuffer = mem_cntrl,
131                                         ruby_system = ruby_system)
132
133        exec("system.dir_cntrl%d = dir_cntrl" % i)
134        dir_cntrl_nodes.append(dir_cntrl)
135
136        cntrl_count += 1
137
138    for i, dma_device in enumerate(dma_devices):
139        #
140        # Create the Ruby objects associated with the dma controller
141        #
142        dma_seq = DMASequencer(version = i,
143                               physMemPort = system.physmem.port,
144                               physmem = system.physmem)
145
146        dma_cntrl = DMA_Controller(version = i,
147                                   cntrl_id = cntrl_count,
148                                   dma_sequencer = dma_seq)
149
150        exec("system.dma_cntrl%d = dma_cntrl" % i)
151        if dma_device.type == 'MemTest':
152            system.dma_cntrl.dma_sequencer.port = dma_device.test
153        else:
154            system.dma_cntrl.dma_sequencer.port = dma_device.dma
155        dma_cntrl.dma_sequencer.port = dma_device.dma
156        dma_cntrl_nodes.append(dma_cntrl)
157
158        cntrl_count += 1
159
160    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
161
162    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
163