MI_example.py revision 7535:7f8213cb2337 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33
34#
35# Note: the cache latency is only used by the sequencer on fast path hits
36#
37class Cache(RubyCache):
38    latency = 3
39
40def create_system(options, phys_mem, piobus, dma_devices):
41
42    if buildEnv['PROTOCOL'] != 'MI_example':
43        panic("This script requires the MI_example protocol to be built.")
44
45    cpu_sequencers = []
46
47    #
48    # The ruby network creation expects the list of nodes in the system to be
49    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
50    # listed before the directory nodes and directory nodes before dma nodes, etc.
51    #
52    l1_cntrl_nodes = []
53    dir_cntrl_nodes = []
54    dma_cntrl_nodes = []
55
56    #
57    # Must create the individual controllers before the network to ensure the
58    # controller constructors are called before the network constructor
59    #
60
61    for i in xrange(options.num_cpus):
62        #
63        # First create the Ruby objects associated with this cpu
64        # Only one cache exists for this protocol, so by default use the L1D
65        # config parameters.
66        #
67        cache = Cache(size = options.l1d_size,
68                      assoc = options.l1d_assoc)
69
70        #
71        # Only one unified L1 cache exists.  Can cache instructions and data.
72        #
73        cpu_seq = RubySequencer(version = i,
74                                icache = cache,
75                                dcache = cache,
76                                physMemPort = phys_mem.port,
77                                physmem = phys_mem)
78
79        if piobus != None:
80            cpu_seq.pio_port = piobus.port
81
82        l1_cntrl = L1Cache_Controller(version = i,
83                                      sequencer = cpu_seq,
84                                      cacheMemory = cache)
85        #
86        # Add controllers and sequencers to the appropriate lists
87        #
88        cpu_sequencers.append(cpu_seq)
89        l1_cntrl_nodes.append(l1_cntrl)
90
91    phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
92    mem_module_size = phys_mem_size / options.num_dirs
93
94    for i in xrange(options.num_dirs):
95        #
96        # Create the Ruby objects associated with the directory controller
97        #
98
99        mem_cntrl = RubyMemoryControl(version = i)
100
101        dir_size = MemorySize('0B')
102        dir_size.value = mem_module_size
103
104        dir_cntrl = Directory_Controller(version = i,
105                                         directory = \
106                                         RubyDirectoryMemory(version = i,
107                                               size = dir_size,
108                                               use_map = options.use_map,
109                                               map_levels = options.map_levels),
110                                         memBuffer = mem_cntrl)
111
112        dir_cntrl_nodes.append(dir_cntrl)
113
114    for i, dma_device in enumerate(dma_devices):
115        #
116        # Create the Ruby objects associated with the dma controller
117        #
118        dma_seq = DMASequencer(version = i,
119                               physMemPort = phys_mem.port,
120                               physmem = phys_mem)
121
122        dma_cntrl = DMA_Controller(version = i,
123                                   dma_sequencer = dma_seq)
124
125        dma_cntrl.dma_sequencer.port = dma_device.dma
126        dma_cntrl_nodes.append(dma_cntrl)
127
128    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
129
130    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
131