MI_example.py revision 10311:ad9c042dce54
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35 36# 37# Note: the cache latency is only used by the sequencer on fast path hits 38# 39class Cache(RubyCache): 40 latency = 3 41 42def define_options(parser): 43 return 44 45def create_system(options, system, dma_ports, ruby_system): 46 47 if buildEnv['PROTOCOL'] != 'MI_example': 48 panic("This script requires the MI_example protocol to be built.") 49 50 cpu_sequencers = [] 51 52 # 53 # The ruby network creation expects the list of nodes in the system to be 54 # consistent with the NetDest list. Therefore the l1 controller nodes must be 55 # listed before the directory nodes and directory nodes before dma nodes, etc. 56 # 57 l1_cntrl_nodes = [] 58 dir_cntrl_nodes = [] 59 dma_cntrl_nodes = [] 60 61 # 62 # Must create the individual controllers before the network to ensure the 63 # controller constructors are called before the network constructor 64 # 65 block_size_bits = int(math.log(options.cacheline_size, 2)) 66 67 for i in xrange(options.num_cpus): 68 # 69 # First create the Ruby objects associated with this cpu 70 # Only one cache exists for this protocol, so by default use the L1D 71 # config parameters. 72 # 73 cache = Cache(size = options.l1d_size, 74 assoc = options.l1d_assoc, 75 start_index_bit = block_size_bits) 76 77 # 78 # Only one unified L1 cache exists. Can cache instructions and data. 79 # 80 l1_cntrl = L1Cache_Controller(version = i, 81 cacheMemory = cache, 82 send_evictions = ( 83 options.cpu_type == "detailed"), 84 transitions_per_cycle = options.ports, 85 clk_domain=system.cpu[i].clk_domain, 86 ruby_system = ruby_system) 87 88 cpu_seq = RubySequencer(version = i, 89 icache = cache, 90 dcache = cache, 91 clk_domain=system.cpu[i].clk_domain, 92 ruby_system = ruby_system) 93 94 l1_cntrl.sequencer = cpu_seq 95 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 96 97 # Add controllers and sequencers to the appropriate lists 98 cpu_sequencers.append(cpu_seq) 99 l1_cntrl_nodes.append(l1_cntrl) 100 101 # Connect the L1 controllers and the network 102 l1_cntrl.requestFromCache = ruby_system.network.slave 103 l1_cntrl.responseFromCache = ruby_system.network.slave 104 l1_cntrl.forwardToCache = ruby_system.network.master 105 l1_cntrl.responseToCache = ruby_system.network.master 106 107 108 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 109 assert(phys_mem_size % options.num_dirs == 0) 110 mem_module_size = phys_mem_size / options.num_dirs 111 112 # Run each of the ruby memory controllers at a ratio of the frequency of 113 # the ruby system. 114 # clk_divider value is a fix to pass regression. 115 ruby_system.memctrl_clk_domain = DerivedClockDomain( 116 clk_domain=ruby_system.clk_domain, 117 clk_divider=3) 118 119 for i in xrange(options.num_dirs): 120 # 121 # Create the Ruby objects associated with the directory controller 122 # 123 124 mem_cntrl = RubyMemoryControl( 125 clk_domain = ruby_system.memctrl_clk_domain, 126 version = i, 127 ruby_system = ruby_system) 128 129 dir_size = MemorySize('0B') 130 dir_size.value = mem_module_size 131 132 dir_cntrl = Directory_Controller(version = i, 133 directory = \ 134 RubyDirectoryMemory( \ 135 version = i, 136 size = dir_size, 137 use_map = options.use_map, 138 map_levels = \ 139 options.map_levels), 140 memBuffer = mem_cntrl, 141 transitions_per_cycle = options.ports, 142 ruby_system = ruby_system) 143 144 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 145 dir_cntrl_nodes.append(dir_cntrl) 146 147 # Connect the directory controllers and the network 148 dir_cntrl.requestToDir = ruby_system.network.master 149 dir_cntrl.dmaRequestToDir = ruby_system.network.master 150 151 dir_cntrl.responseFromDir = ruby_system.network.slave 152 dir_cntrl.dmaResponseFromDir = ruby_system.network.slave 153 dir_cntrl.forwardFromDir = ruby_system.network.slave 154 155 156 for i, dma_port in enumerate(dma_ports): 157 # 158 # Create the Ruby objects associated with the dma controller 159 # 160 dma_seq = DMASequencer(version = i, 161 ruby_system = ruby_system) 162 163 dma_cntrl = DMA_Controller(version = i, 164 dma_sequencer = dma_seq, 165 transitions_per_cycle = options.ports, 166 ruby_system = ruby_system) 167 168 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 169 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 170 dma_cntrl_nodes.append(dma_cntrl) 171 172 # Connect the directory controllers and the network 173 dma_cntrl.requestToDir = ruby_system.network.master 174 dma_cntrl.responseFromDir = ruby_system.network.slave 175 176 177 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 178 topology = create_topology(all_cntrls, options) 179 return (cpu_sequencers, dir_cntrl_nodes, topology) 180