MESI_Two_Level.py revision 9468 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40    latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46    latency = 15
47
48def define_options(parser):
49    return
50
51def create_system(options, system, piobus, dma_ports, ruby_system):
52
53    if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
54        panic("This script requires the MESI_CMP_directory protocol to be built.")
55
56    cpu_sequencers = []
57
58    #
59    # The ruby network creation expects the list of nodes in the system to be
60    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
61    # listed before the directory nodes and directory nodes before dma nodes, etc.
62    #
63    l1_cntrl_nodes = []
64    l2_cntrl_nodes = []
65    dir_cntrl_nodes = []
66    dma_cntrl_nodes = []
67
68    #
69    # Must create the individual controllers before the network to ensure the
70    # controller constructors are called before the network constructor
71    #
72    l2_bits = int(math.log(options.num_l2caches, 2))
73    block_size_bits = int(math.log(options.cacheline_size, 2))
74
75    cntrl_count = 0
76
77    for i in xrange(options.num_cpus):
78        #
79        # First create the Ruby objects associated with this cpu
80        #
81        l1i_cache = L1Cache(size = options.l1i_size,
82                            assoc = options.l1i_assoc,
83                            start_index_bit = block_size_bits,
84                            is_icache = True)
85        l1d_cache = L1Cache(size = options.l1d_size,
86                            assoc = options.l1d_assoc,
87                            start_index_bit = block_size_bits,
88                            is_icache = False)
89
90        prefetcher = RubyPrefetcher.Prefetcher()
91
92        l1_cntrl = L1Cache_Controller(version = i,
93                                      cntrl_id = cntrl_count,
94                                      L1IcacheMemory = l1i_cache,
95                                      L1DcacheMemory = l1d_cache,
96                                      l2_select_num_bits = l2_bits,
97                                      send_evictions = (
98                                          options.cpu_type == "detailed"),
99                                      prefetcher = prefetcher,
100                                      ruby_system = ruby_system,
101                                      enable_prefetch = False)
102
103        cpu_seq = RubySequencer(version = i,
104                                icache = l1i_cache,
105                                dcache = l1d_cache,
106                                ruby_system = ruby_system)
107
108        l1_cntrl.sequencer = cpu_seq
109
110        if piobus != None:
111            cpu_seq.pio_port = piobus.slave
112
113        exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
114
115        #
116        # Add controllers and sequencers to the appropriate lists
117        #
118        cpu_sequencers.append(cpu_seq)
119        l1_cntrl_nodes.append(l1_cntrl)
120
121        cntrl_count += 1
122
123    l2_index_start = block_size_bits + l2_bits
124
125    for i in xrange(options.num_l2caches):
126        #
127        # First create the Ruby objects associated with this cpu
128        #
129        l2_cache = L2Cache(size = options.l2_size,
130                           assoc = options.l2_assoc,
131                           start_index_bit = l2_index_start)
132
133        l2_cntrl = L2Cache_Controller(version = i,
134                                      cntrl_id = cntrl_count,
135                                      L2cacheMemory = l2_cache,
136                                      ruby_system = ruby_system)
137
138        exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
139        l2_cntrl_nodes.append(l2_cntrl)
140
141        cntrl_count += 1
142
143    phys_mem_size = sum(map(lambda mem: mem.range.size(),
144                            system.memories.unproxy(system)))
145    mem_module_size = phys_mem_size / options.num_dirs
146
147    for i in xrange(options.num_dirs):
148        #
149        # Create the Ruby objects associated with the directory controller
150        #
151
152        mem_cntrl = RubyMemoryControl(version = i,
153                                      ruby_system = ruby_system)
154
155        dir_size = MemorySize('0B')
156        dir_size.value = mem_module_size
157
158        dir_cntrl = Directory_Controller(version = i,
159                                         cntrl_id = cntrl_count,
160                                         directory = \
161                                         RubyDirectoryMemory(version = i,
162                                                             size = dir_size,
163                                                             use_map =
164                                                           options.use_map),
165                                         memBuffer = mem_cntrl,
166                                         ruby_system = ruby_system)
167
168        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
169        dir_cntrl_nodes.append(dir_cntrl)
170
171        cntrl_count += 1
172
173    for i, dma_port in enumerate(dma_ports):
174        #
175        # Create the Ruby objects associated with the dma controller
176        #
177        dma_seq = DMASequencer(version = i,
178                               ruby_system = ruby_system)
179
180        dma_cntrl = DMA_Controller(version = i,
181                                   cntrl_id = cntrl_count,
182                                   dma_sequencer = dma_seq,
183                                   ruby_system = ruby_system)
184
185        exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
186        exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
187        dma_cntrl_nodes.append(dma_cntrl)
188        cntrl_count += 1
189
190    all_cntrls = l1_cntrl_nodes + \
191                 l2_cntrl_nodes + \
192                 dir_cntrl_nodes + \
193                 dma_cntrl_nodes
194
195    topology = create_topology(all_cntrls, options)
196
197    return (cpu_sequencers, dir_cntrl_nodes, topology)
198