MESI_Two_Level.py revision 9319
110453SAndrew.Bardsley@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 210453SAndrew.Bardsley@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 310453SAndrew.Bardsley@arm.com# All rights reserved. 410453SAndrew.Bardsley@arm.com# 510453SAndrew.Bardsley@arm.com# Redistribution and use in source and binary forms, with or without 610453SAndrew.Bardsley@arm.com# modification, are permitted provided that the following conditions are 710453SAndrew.Bardsley@arm.com# met: redistributions of source code must retain the above copyright 810453SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer; 910453SAndrew.Bardsley@arm.com# redistributions in binary form must reproduce the above copyright 1010453SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer in the 1110453SAndrew.Bardsley@arm.com# documentation and/or other materials provided with the distribution; 1210453SAndrew.Bardsley@arm.com# neither the name of the copyright holders nor the names of its 1310453SAndrew.Bardsley@arm.com# contributors may be used to endorse or promote products derived from 1410453SAndrew.Bardsley@arm.com# this software without specific prior written permission. 1510453SAndrew.Bardsley@arm.com# 1610453SAndrew.Bardsley@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710453SAndrew.Bardsley@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810453SAndrew.Bardsley@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910453SAndrew.Bardsley@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010453SAndrew.Bardsley@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110453SAndrew.Bardsley@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210453SAndrew.Bardsley@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310453SAndrew.Bardsley@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410453SAndrew.Bardsley@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510453SAndrew.Bardsley@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610453SAndrew.Bardsley@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710453SAndrew.Bardsley@arm.com# 2810453SAndrew.Bardsley@arm.com# Authors: Brad Beckmann 2910453SAndrew.Bardsley@arm.com 3010453SAndrew.Bardsley@arm.comimport math 3110453SAndrew.Bardsley@arm.comimport m5 3211793Sbrandon.potter@amd.comfrom m5.objects import * 3311793Sbrandon.potter@amd.comfrom m5.defines import buildEnv 3410453SAndrew.Bardsley@arm.comfrom Ruby import create_topology 3510453SAndrew.Bardsley@arm.com 3610453SAndrew.Bardsley@arm.com# 3710453SAndrew.Bardsley@arm.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 3810453SAndrew.Bardsley@arm.com# 3910453SAndrew.Bardsley@arm.comclass L1Cache(RubyCache): 4010453SAndrew.Bardsley@arm.com latency = 3 4110453SAndrew.Bardsley@arm.com 4210453SAndrew.Bardsley@arm.com# 4310453SAndrew.Bardsley@arm.com# Note: the L2 Cache latency is not currently used 4410453SAndrew.Bardsley@arm.com# 4510453SAndrew.Bardsley@arm.comclass L2Cache(RubyCache): 4610453SAndrew.Bardsley@arm.com latency = 15 4710453SAndrew.Bardsley@arm.com 4810453SAndrew.Bardsley@arm.comdef define_options(parser): 4910453SAndrew.Bardsley@arm.com return 5010453SAndrew.Bardsley@arm.com 5110453SAndrew.Bardsley@arm.comdef create_system(options, system, piobus, dma_ports, ruby_system): 52 53 if buildEnv['PROTOCOL'] != 'MESI_CMP_directory': 54 panic("This script requires the MESI_CMP_directory protocol to be built.") 55 56 cpu_sequencers = [] 57 58 # 59 # The ruby network creation expects the list of nodes in the system to be 60 # consistent with the NetDest list. Therefore the l1 controller nodes must be 61 # listed before the directory nodes and directory nodes before dma nodes, etc. 62 # 63 l1_cntrl_nodes = [] 64 l2_cntrl_nodes = [] 65 dir_cntrl_nodes = [] 66 dma_cntrl_nodes = [] 67 68 # 69 # Must create the individual controllers before the network to ensure the 70 # controller constructors are called before the network constructor 71 # 72 l2_bits = int(math.log(options.num_l2caches, 2)) 73 block_size_bits = int(math.log(options.cacheline_size, 2)) 74 75 cntrl_count = 0 76 77 for i in xrange(options.num_cpus): 78 # 79 # First create the Ruby objects associated with this cpu 80 # 81 l1i_cache = L1Cache(size = options.l1i_size, 82 assoc = options.l1i_assoc, 83 start_index_bit = block_size_bits, 84 is_icache = True) 85 l1d_cache = L1Cache(size = options.l1d_size, 86 assoc = options.l1d_assoc, 87 start_index_bit = block_size_bits, 88 is_icache = False) 89 90 l1_cntrl = L1Cache_Controller(version = i, 91 cntrl_id = cntrl_count, 92 L1IcacheMemory = l1i_cache, 93 L1DcacheMemory = l1d_cache, 94 l2_select_num_bits = l2_bits, 95 send_evictions = ( 96 options.cpu_type == "detailed"), 97 ruby_system = ruby_system) 98 99 cpu_seq = RubySequencer(version = i, 100 icache = l1i_cache, 101 dcache = l1d_cache, 102 ruby_system = ruby_system) 103 104 l1_cntrl.sequencer = cpu_seq 105 106 if piobus != None: 107 cpu_seq.pio_port = piobus.slave 108 109 exec("system.l1_cntrl%d = l1_cntrl" % i) 110 111 # 112 # Add controllers and sequencers to the appropriate lists 113 # 114 cpu_sequencers.append(cpu_seq) 115 l1_cntrl_nodes.append(l1_cntrl) 116 117 cntrl_count += 1 118 119 l2_index_start = block_size_bits + l2_bits 120 121 for i in xrange(options.num_l2caches): 122 # 123 # First create the Ruby objects associated with this cpu 124 # 125 l2_cache = L2Cache(size = options.l2_size, 126 assoc = options.l2_assoc, 127 start_index_bit = l2_index_start) 128 129 l2_cntrl = L2Cache_Controller(version = i, 130 cntrl_id = cntrl_count, 131 L2cacheMemory = l2_cache, 132 ruby_system = ruby_system) 133 134 exec("system.l2_cntrl%d = l2_cntrl" % i) 135 l2_cntrl_nodes.append(l2_cntrl) 136 137 cntrl_count += 1 138 139 phys_mem_size = sum(map(lambda mem: mem.range.size(), 140 system.memories.unproxy(system))) 141 mem_module_size = phys_mem_size / options.num_dirs 142 143 for i in xrange(options.num_dirs): 144 # 145 # Create the Ruby objects associated with the directory controller 146 # 147 148 mem_cntrl = RubyMemoryControl(version = i, 149 ruby_system = ruby_system) 150 151 dir_size = MemorySize('0B') 152 dir_size.value = mem_module_size 153 154 dir_cntrl = Directory_Controller(version = i, 155 cntrl_id = cntrl_count, 156 directory = \ 157 RubyDirectoryMemory(version = i, 158 size = dir_size, 159 use_map = 160 options.use_map), 161 memBuffer = mem_cntrl, 162 ruby_system = ruby_system) 163 164 exec("system.dir_cntrl%d = dir_cntrl" % i) 165 dir_cntrl_nodes.append(dir_cntrl) 166 167 cntrl_count += 1 168 169 for i, dma_port in enumerate(dma_ports): 170 # 171 # Create the Ruby objects associated with the dma controller 172 # 173 dma_seq = DMASequencer(version = i, 174 ruby_system = ruby_system) 175 176 dma_cntrl = DMA_Controller(version = i, 177 cntrl_id = cntrl_count, 178 dma_sequencer = dma_seq, 179 ruby_system = ruby_system) 180 181 exec("system.dma_cntrl%d = dma_cntrl" % i) 182 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 183 dma_cntrl_nodes.append(dma_cntrl) 184 cntrl_count += 1 185 186 all_cntrls = l1_cntrl_nodes + \ 187 l2_cntrl_nodes + \ 188 dir_cntrl_nodes + \ 189 dma_cntrl_nodes 190 191 topology = create_topology(all_cntrls, options) 192 193 return (cpu_sequencers, dir_cntrl_nodes, topology) 194