MESI_Two_Level.py revision 8718
15325Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 25325Sgblack@eecs.umich.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 35325Sgblack@eecs.umich.edu# All rights reserved. 45325Sgblack@eecs.umich.edu# 55325Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 65325Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 75325Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 85325Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 95325Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 105325Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 115325Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 125325Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 135325Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 145325Sgblack@eecs.umich.edu# this software without specific prior written permission. 155325Sgblack@eecs.umich.edu# 165325Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175325Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185325Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195325Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205325Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215325Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225325Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235325Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245325Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255325Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265325Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275325Sgblack@eecs.umich.edu# 285325Sgblack@eecs.umich.edu# Authors: Brad Beckmann 295325Sgblack@eecs.umich.edu 305149Sgblack@eecs.umich.eduimport math 315149Sgblack@eecs.umich.eduimport m5 325149Sgblack@eecs.umich.edufrom m5.objects import * 335149Sgblack@eecs.umich.edufrom m5.defines import buildEnv 345149Sgblack@eecs.umich.edu 355149Sgblack@eecs.umich.edu# 365149Sgblack@eecs.umich.edu# Note: the L1 Cache latency is only used by the sequencer on fast path hits 375149Sgblack@eecs.umich.edu# 385149Sgblack@eecs.umich.educlass L1Cache(RubyCache): 395149Sgblack@eecs.umich.edu latency = 3 405149Sgblack@eecs.umich.edu 415149Sgblack@eecs.umich.edu# 425149Sgblack@eecs.umich.edu# Note: the L2 Cache latency is not currently used 435149Sgblack@eecs.umich.edu# 445149Sgblack@eecs.umich.educlass L2Cache(RubyCache): 455149Sgblack@eecs.umich.edu latency = 15 465149Sgblack@eecs.umich.edu 475149Sgblack@eecs.umich.edudef define_options(parser): 485149Sgblack@eecs.umich.edu return 495149Sgblack@eecs.umich.edu 505149Sgblack@eecs.umich.edudef create_system(options, system, piobus, dma_devices, ruby_system): 515149Sgblack@eecs.umich.edu 525149Sgblack@eecs.umich.edu if buildEnv['PROTOCOL'] != 'MESI_CMP_directory': 535149Sgblack@eecs.umich.edu panic("This script requires the MESI_CMP_directory protocol to be built.") 545149Sgblack@eecs.umich.edu 555149Sgblack@eecs.umich.edu cpu_sequencers = [] 565149Sgblack@eecs.umich.edu 575149Sgblack@eecs.umich.edu # 585149Sgblack@eecs.umich.edu # The ruby network creation expects the list of nodes in the system to be 595149Sgblack@eecs.umich.edu # consistent with the NetDest list. Therefore the l1 controller nodes must be 605149Sgblack@eecs.umich.edu # listed before the directory nodes and directory nodes before dma nodes, etc. 615149Sgblack@eecs.umich.edu # 625149Sgblack@eecs.umich.edu l1_cntrl_nodes = [] 635149Sgblack@eecs.umich.edu l2_cntrl_nodes = [] 645149Sgblack@eecs.umich.edu dir_cntrl_nodes = [] 655149Sgblack@eecs.umich.edu dma_cntrl_nodes = [] 665149Sgblack@eecs.umich.edu 675149Sgblack@eecs.umich.edu # 685149Sgblack@eecs.umich.edu # Must create the individual controllers before the network to ensure the 695149Sgblack@eecs.umich.edu # controller constructors are called before the network constructor 705149Sgblack@eecs.umich.edu # 715149Sgblack@eecs.umich.edu l2_bits = int(math.log(options.num_l2caches, 2)) 725149Sgblack@eecs.umich.edu block_size_bits = int(math.log(options.cacheline_size, 2)) 735149Sgblack@eecs.umich.edu 745149Sgblack@eecs.umich.edu cntrl_count = 0 755149Sgblack@eecs.umich.edu 765149Sgblack@eecs.umich.edu for i in xrange(options.num_cpus): 775149Sgblack@eecs.umich.edu # 785149Sgblack@eecs.umich.edu # First create the Ruby objects associated with this cpu 795149Sgblack@eecs.umich.edu # 805149Sgblack@eecs.umich.edu l1i_cache = L1Cache(size = options.l1i_size, 815149Sgblack@eecs.umich.edu assoc = options.l1i_assoc, 825149Sgblack@eecs.umich.edu start_index_bit = block_size_bits) 835149Sgblack@eecs.umich.edu l1d_cache = L1Cache(size = options.l1d_size, 845149Sgblack@eecs.umich.edu assoc = options.l1d_assoc, 855243Sgblack@eecs.umich.edu start_index_bit = block_size_bits) 865149Sgblack@eecs.umich.edu 875149Sgblack@eecs.umich.edu l1_cntrl = L1Cache_Controller(version = i, 885149Sgblack@eecs.umich.edu cntrl_id = cntrl_count, 895149Sgblack@eecs.umich.edu L1IcacheMemory = l1i_cache, 905149Sgblack@eecs.umich.edu L1DcacheMemory = l1d_cache, 915149Sgblack@eecs.umich.edu l2_select_num_bits = l2_bits, 925149Sgblack@eecs.umich.edu send_evictions = ( 935149Sgblack@eecs.umich.edu options.cpu_type == "detailed"), 945243Sgblack@eecs.umich.edu ruby_system = ruby_system) 955149Sgblack@eecs.umich.edu 965149Sgblack@eecs.umich.edu cpu_seq = RubySequencer(version = i, 975149Sgblack@eecs.umich.edu icache = l1i_cache, 985325Sgblack@eecs.umich.edu dcache = l1d_cache, 995325Sgblack@eecs.umich.edu physMemPort = system.physmem.port, 1005149Sgblack@eecs.umich.edu physmem = system.physmem, 1015149Sgblack@eecs.umich.edu ruby_system = ruby_system) 1025409Sgblack@eecs.umich.edu 1035409Sgblack@eecs.umich.edu l1_cntrl.sequencer = cpu_seq 1045409Sgblack@eecs.umich.edu 1055409Sgblack@eecs.umich.edu if piobus != None: 1065409Sgblack@eecs.umich.edu cpu_seq.pio_port = piobus.port 1075409Sgblack@eecs.umich.edu 1085409Sgblack@eecs.umich.edu exec("system.l1_cntrl%d = l1_cntrl" % i) 1095409Sgblack@eecs.umich.edu 1105149Sgblack@eecs.umich.edu # 111 # Add controllers and sequencers to the appropriate lists 112 # 113 cpu_sequencers.append(cpu_seq) 114 l1_cntrl_nodes.append(l1_cntrl) 115 116 cntrl_count += 1 117 118 l2_index_start = block_size_bits + l2_bits 119 120 for i in xrange(options.num_l2caches): 121 # 122 # First create the Ruby objects associated with this cpu 123 # 124 l2_cache = L2Cache(size = options.l2_size, 125 assoc = options.l2_assoc, 126 start_index_bit = l2_index_start) 127 128 l2_cntrl = L2Cache_Controller(version = i, 129 cntrl_id = cntrl_count, 130 L2cacheMemory = l2_cache, 131 ruby_system = ruby_system) 132 133 exec("system.l2_cntrl%d = l2_cntrl" % i) 134 l2_cntrl_nodes.append(l2_cntrl) 135 136 cntrl_count += 1 137 138 phys_mem_size = long(system.physmem.range.second) - \ 139 long(system.physmem.range.first) + 1 140 mem_module_size = phys_mem_size / options.num_dirs 141 142 for i in xrange(options.num_dirs): 143 # 144 # Create the Ruby objects associated with the directory controller 145 # 146 147 mem_cntrl = RubyMemoryControl(version = i) 148 149 dir_size = MemorySize('0B') 150 dir_size.value = mem_module_size 151 152 dir_cntrl = Directory_Controller(version = i, 153 cntrl_id = cntrl_count, 154 directory = \ 155 RubyDirectoryMemory(version = i, 156 size = dir_size, 157 use_map = 158 options.use_map), 159 memBuffer = mem_cntrl, 160 ruby_system = ruby_system) 161 162 exec("system.dir_cntrl%d = dir_cntrl" % i) 163 dir_cntrl_nodes.append(dir_cntrl) 164 165 cntrl_count += 1 166 167 for i, dma_device in enumerate(dma_devices): 168 # 169 # Create the Ruby objects associated with the dma controller 170 # 171 dma_seq = DMASequencer(version = i, 172 physMemPort = system.physmem.port, 173 physmem = system.physmem, 174 ruby_system = ruby_system) 175 176 dma_cntrl = DMA_Controller(version = i, 177 cntrl_id = cntrl_count, 178 dma_sequencer = dma_seq, 179 ruby_system = ruby_system) 180 181 exec("system.dma_cntrl%d = dma_cntrl" % i) 182 if dma_device.type == 'MemTest': 183 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 184 else: 185 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 186 dma_cntrl_nodes.append(dma_cntrl) 187 188 cntrl_count += 1 189 190 all_cntrls = l1_cntrl_nodes + \ 191 l2_cntrl_nodes + \ 192 dir_cntrl_nodes + \ 193 dma_cntrl_nodes 194 195 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 196