MESI_Two_Level.py revision 11019
16915SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 26915SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 36915SN/A# All rights reserved. 46915SN/A# 56915SN/A# Redistribution and use in source and binary forms, with or without 66915SN/A# modification, are permitted provided that the following conditions are 76915SN/A# met: redistributions of source code must retain the above copyright 86915SN/A# notice, this list of conditions and the following disclaimer; 96915SN/A# redistributions in binary form must reproduce the above copyright 106915SN/A# notice, this list of conditions and the following disclaimer in the 116915SN/A# documentation and/or other materials provided with the distribution; 126915SN/A# neither the name of the copyright holders nor the names of its 136915SN/A# contributors may be used to endorse or promote products derived from 146915SN/A# this software without specific prior written permission. 156915SN/A# 166915SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176915SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186915SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196915SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206915SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216915SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226915SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236915SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246915SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256915SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266915SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276915SN/A# 286915SN/A# Authors: Brad Beckmann 296915SN/A 306915SN/Aimport math 316915SN/Aimport m5 326915SN/Afrom m5.objects import * 336915SN/Afrom m5.defines import buildEnv 349100SN/Afrom Ruby import create_topology 3510529Smorr@cs.wisc.edufrom Ruby import send_evicts 366915SN/A 376915SN/A# 3811019Sjthestness@gmail.com# Declare caches used by the protocol 396915SN/A# 4011019Sjthestness@gmail.comclass L1Cache(RubyCache): pass 4111019Sjthestness@gmail.comclass L2Cache(RubyCache): pass 426915SN/A 437538SN/Adef define_options(parser): 447538SN/A return 457538SN/A 4610519Snilay@cs.wisc.edudef create_system(options, full_system, system, dma_ports, ruby_system): 4710007Snilay@cs.wisc.edu 4810007Snilay@cs.wisc.edu if buildEnv['PROTOCOL'] != 'MESI_Two_Level': 4910007Snilay@cs.wisc.edu fatal("This script requires the MESI_Two_Level protocol to be built.") 506915SN/A 516915SN/A cpu_sequencers = [] 5210007Snilay@cs.wisc.edu 536915SN/A # 546915SN/A # The ruby network creation expects the list of nodes in the system to be 556915SN/A # consistent with the NetDest list. Therefore the l1 controller nodes must be 566915SN/A # listed before the directory nodes and directory nodes before dma nodes, etc. 576915SN/A # 586915SN/A l1_cntrl_nodes = [] 596915SN/A l2_cntrl_nodes = [] 606915SN/A dir_cntrl_nodes = [] 616915SN/A dma_cntrl_nodes = [] 626915SN/A 636915SN/A # 646915SN/A # Must create the individual controllers before the network to ensure the 656915SN/A # controller constructors are called before the network constructor 666915SN/A # 678180SN/A l2_bits = int(math.log(options.num_l2caches, 2)) 688180SN/A block_size_bits = int(math.log(options.cacheline_size, 2)) 6910007Snilay@cs.wisc.edu 706915SN/A for i in xrange(options.num_cpus): 716915SN/A # 726915SN/A # First create the Ruby objects associated with this cpu 736915SN/A # 746915SN/A l1i_cache = L1Cache(size = options.l1i_size, 758180SN/A assoc = options.l1i_assoc, 769319SN/A start_index_bit = block_size_bits, 779319SN/A is_icache = True) 786915SN/A l1d_cache = L1Cache(size = options.l1d_size, 798180SN/A assoc = options.l1d_assoc, 809319SN/A start_index_bit = block_size_bits, 819319SN/A is_icache = False) 826915SN/A 839366SN/A prefetcher = RubyPrefetcher.Prefetcher() 849366SN/A 858322SN/A l1_cntrl = L1Cache_Controller(version = i, 869696SN/A L1Icache = l1i_cache, 879696SN/A L1Dcache = l1d_cache, 888436SN/A l2_select_num_bits = l2_bits, 8910529Smorr@cs.wisc.edu send_evictions = send_evicts(options), 909366SN/A prefetcher = prefetcher, 919366SN/A ruby_system = ruby_system, 9210300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 939841SN/A transitions_per_cycle=options.ports, 949366SN/A enable_prefetch = False) 958322SN/A 967015SN/A cpu_seq = RubySequencer(version = i, 977015SN/A icache = l1i_cache, 986915SN/A dcache = l1d_cache, 9910300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 1008436SN/A ruby_system = ruby_system) 1016915SN/A 1028322SN/A l1_cntrl.sequencer = cpu_seq 1039468SN/A exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 10410007Snilay@cs.wisc.edu 1056915SN/A # Add controllers and sequencers to the appropriate lists 1066915SN/A cpu_sequencers.append(cpu_seq) 1076915SN/A l1_cntrl_nodes.append(l1_cntrl) 10810007Snilay@cs.wisc.edu 10910311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 11010311Snilay@cs.wisc.edu l1_cntrl.requestFromL1Cache = ruby_system.network.slave 11110311Snilay@cs.wisc.edu l1_cntrl.responseFromL1Cache = ruby_system.network.slave 11210311Snilay@cs.wisc.edu l1_cntrl.unblockFromL1Cache = ruby_system.network.slave 11310311Snilay@cs.wisc.edu 11410311Snilay@cs.wisc.edu l1_cntrl.requestToL1Cache = ruby_system.network.master 11510311Snilay@cs.wisc.edu l1_cntrl.responseToL1Cache = ruby_system.network.master 11610311Snilay@cs.wisc.edu 11710311Snilay@cs.wisc.edu 1188180SN/A l2_index_start = block_size_bits + l2_bits 1198180SN/A 1206915SN/A for i in xrange(options.num_l2caches): 1216915SN/A # 1226915SN/A # First create the Ruby objects associated with this cpu 1236915SN/A # 1246915SN/A l2_cache = L2Cache(size = options.l2_size, 1258180SN/A assoc = options.l2_assoc, 1268180SN/A start_index_bit = l2_index_start) 1276915SN/A 1286915SN/A l2_cntrl = L2Cache_Controller(version = i, 1299696SN/A L2cache = l2_cache, 1309841SN/A transitions_per_cycle=options.ports, 1318436SN/A ruby_system = ruby_system) 13210007Snilay@cs.wisc.edu 1339468SN/A exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1346915SN/A l2_cntrl_nodes.append(l2_cntrl) 13510007Snilay@cs.wisc.edu 13610311Snilay@cs.wisc.edu # Connect the L2 controllers and the network 13710311Snilay@cs.wisc.edu l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave 13810311Snilay@cs.wisc.edu l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 13910311Snilay@cs.wisc.edu l2_cntrl.responseFromL2Cache = ruby_system.network.slave 14010311Snilay@cs.wisc.edu 14110311Snilay@cs.wisc.edu l2_cntrl.unblockToL2Cache = ruby_system.network.master 14210311Snilay@cs.wisc.edu l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 14310311Snilay@cs.wisc.edu l2_cntrl.responseToL2Cache = ruby_system.network.master 14410311Snilay@cs.wisc.edu 14510311Snilay@cs.wisc.edu 1469826SN/A phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1479798SN/A assert(phys_mem_size % options.num_dirs == 0) 1486915SN/A mem_module_size = phys_mem_size / options.num_dirs 1496915SN/A 15010311Snilay@cs.wisc.edu 1519793SN/A # Run each of the ruby memory controllers at a ratio of the frequency of 1529793SN/A # the ruby system 1539793SN/A # clk_divider value is a fix to pass regression. 1549793SN/A ruby_system.memctrl_clk_domain = DerivedClockDomain( 1559793SN/A clk_domain=ruby_system.clk_domain, 1569793SN/A clk_divider=3) 1579793SN/A 1586915SN/A for i in xrange(options.num_dirs): 1596915SN/A dir_size = MemorySize('0B') 1606915SN/A dir_size.value = mem_module_size 1616915SN/A 1626915SN/A dir_cntrl = Directory_Controller(version = i, 16310524Snilay@cs.wisc.edu directory = RubyDirectoryMemory( 16410524Snilay@cs.wisc.edu version = i, size = dir_size), 1659841SN/A transitions_per_cycle = options.ports, 1668436SN/A ruby_system = ruby_system) 1676915SN/A 1689468SN/A exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1696915SN/A dir_cntrl_nodes.append(dir_cntrl) 1706915SN/A 17110311Snilay@cs.wisc.edu # Connect the directory controllers and the network 17210311Snilay@cs.wisc.edu dir_cntrl.requestToDir = ruby_system.network.master 17310311Snilay@cs.wisc.edu dir_cntrl.responseToDir = ruby_system.network.master 17410311Snilay@cs.wisc.edu dir_cntrl.responseFromDir = ruby_system.network.slave 17510311Snilay@cs.wisc.edu 17610311Snilay@cs.wisc.edu 1778929SN/A for i, dma_port in enumerate(dma_ports): 1786915SN/A # Create the Ruby objects associated with the dma controller 1796915SN/A dma_seq = DMASequencer(version = i, 18010519Snilay@cs.wisc.edu ruby_system = ruby_system, 18110519Snilay@cs.wisc.edu slave = dma_port) 18210007Snilay@cs.wisc.edu 1836915SN/A dma_cntrl = DMA_Controller(version = i, 1848477SN/A dma_sequencer = dma_seq, 1859841SN/A transitions_per_cycle = options.ports, 1868477SN/A ruby_system = ruby_system) 1876915SN/A 1889468SN/A exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 1896915SN/A dma_cntrl_nodes.append(dma_cntrl) 1908257SN/A 19110311Snilay@cs.wisc.edu # Connect the dma controller to the network 19210311Snilay@cs.wisc.edu dma_cntrl.responseFromDir = ruby_system.network.master 19310311Snilay@cs.wisc.edu dma_cntrl.requestToDir = ruby_system.network.slave 19410311Snilay@cs.wisc.edu 1956915SN/A all_cntrls = l1_cntrl_nodes + \ 1966915SN/A l2_cntrl_nodes + \ 1976915SN/A dir_cntrl_nodes + \ 1986915SN/A dma_cntrl_nodes 1996915SN/A 20010519Snilay@cs.wisc.edu # Create the io controller and the sequencer 20110519Snilay@cs.wisc.edu if full_system: 20210519Snilay@cs.wisc.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 20310519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 20410519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 20510519Snilay@cs.wisc.edu dma_sequencer = io_seq, 20610519Snilay@cs.wisc.edu ruby_system = ruby_system) 20710519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 20810519Snilay@cs.wisc.edu 20910519Snilay@cs.wisc.edu # Connect the dma controller to the network 21010519Snilay@cs.wisc.edu io_controller.responseFromDir = ruby_system.network.master 21110519Snilay@cs.wisc.edu io_controller.requestToDir = ruby_system.network.slave 21210519Snilay@cs.wisc.edu 21310519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 21410519Snilay@cs.wisc.edu 2159100SN/A topology = create_topology(all_cntrls, options) 2169100SN/A return (cpu_sequencers, dir_cntrl_nodes, topology) 217