MESI_Three_Level.py revision 10652:e5936c2d53a0
12810Srdreslin@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 210343SCurtis.Dunham@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 38702Sandreas.hansson@arm.com# Copyright (c) 2013 Mark D. Hill and David A. Wood 48702Sandreas.hansson@arm.com# All rights reserved. 58702Sandreas.hansson@arm.com# 68702Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 78702Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 88702Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 98702Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 108702Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 118702Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 128702Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 138702Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 142810Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from 152810Srdreslin@umich.edu# this software without specific prior written permission. 162810Srdreslin@umich.edu# 172810Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182810Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192810Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202810Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212810Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222810Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232810Srdreslin@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242810Srdreslin@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252810Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262810Srdreslin@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272810Srdreslin@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282810Srdreslin@umich.edu# 292810Srdreslin@umich.edu# Authors: Brad Beckmann 302810Srdreslin@umich.edu# Nilay Vaish 312810Srdreslin@umich.edu 322810Srdreslin@umich.eduimport math 332810Srdreslin@umich.eduimport m5 342810Srdreslin@umich.edufrom m5.objects import * 352810Srdreslin@umich.edufrom m5.defines import buildEnv 362810Srdreslin@umich.edufrom Ruby import create_topology 372810Srdreslin@umich.edufrom Ruby import send_evicts 382810Srdreslin@umich.edu 392810Srdreslin@umich.edu# 402810Srdreslin@umich.edu# Note: the L1 Cache latency is only used by the sequencer on fast path hits 412810Srdreslin@umich.edu# 422810Srdreslin@umich.educlass L0Cache(RubyCache): 434458Sstever@eecs.umich.edu latency = 1 448856Sandreas.hansson@arm.com 452810Srdreslin@umich.educlass L1Cache(RubyCache): 462810Srdreslin@umich.edu latency = 5 472810Srdreslin@umich.edu 482810Srdreslin@umich.edu# 492810Srdreslin@umich.edu# Note: the L2 Cache latency is not currently used 502810Srdreslin@umich.edu# 512810Srdreslin@umich.educlass L2Cache(RubyCache): 5211051Sandreas.hansson@arm.com latency = 15 5311051Sandreas.hansson@arm.com 542810Srdreslin@umich.edudef define_options(parser): 552810Srdreslin@umich.edu parser.add_option("--num-clusters", type="int", default=1, 565338Sstever@gmail.com help="number of clusters in a design in which there are shared\ 575338Sstever@gmail.com caches private to clusters") 585338Sstever@gmail.com return 5910815Sdavid.guillen@arm.com 6011053Sandreas.hansson@arm.comdef create_system(options, full_system, system, dma_ports, ruby_system): 614458Sstever@eecs.umich.edu 624458Sstever@eecs.umich.edu if buildEnv['PROTOCOL'] != 'MESI_Three_Level': 632813Srdreslin@umich.edu fatal("This script requires the MESI_Three_Level protocol to be built.") 643861Sstever@eecs.umich.edu 652810Srdreslin@umich.edu cpu_sequencers = [] 662810Srdreslin@umich.edu 672810Srdreslin@umich.edu # 682810Srdreslin@umich.edu # The ruby network creation expects the list of nodes in the system to be 699264Sdjordje.kovacevic@arm.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 702810Srdreslin@umich.edu # listed before the directory nodes and directory nodes before dma nodes, etc. 712810Srdreslin@umich.edu # 722810Srdreslin@umich.edu l0_cntrl_nodes = [] 732810Srdreslin@umich.edu l1_cntrl_nodes = [] 7410815Sdavid.guillen@arm.com l2_cntrl_nodes = [] 7510815Sdavid.guillen@arm.com dir_cntrl_nodes = [] 7610815Sdavid.guillen@arm.com dma_cntrl_nodes = [] 772810Srdreslin@umich.edu 782810Srdreslin@umich.edu assert (options.num_cpus % options.num_clusters == 0) 792810Srdreslin@umich.edu num_cpus_per_cluster = options.num_cpus / options.num_clusters 808856Sandreas.hansson@arm.com 818856Sandreas.hansson@arm.com assert (options.num_l2caches % options.num_clusters == 0) 828856Sandreas.hansson@arm.com num_l2caches_per_cluster = options.num_l2caches / options.num_clusters 838856Sandreas.hansson@arm.com 848856Sandreas.hansson@arm.com l2_bits = int(math.log(num_l2caches_per_cluster, 2)) 853738Sstever@eecs.umich.edu block_size_bits = int(math.log(options.cacheline_size, 2)) 868856Sandreas.hansson@arm.com l2_index_start = block_size_bits + l2_bits 873738Sstever@eecs.umich.edu 888856Sandreas.hansson@arm.com # 8910815Sdavid.guillen@arm.com # Must create the individual controllers before the network to ensure the 903738Sstever@eecs.umich.edu # controller constructors are called before the network constructor 918856Sandreas.hansson@arm.com # 924478Sstever@eecs.umich.edu for i in xrange(options.num_clusters): 938975Sandreas.hansson@arm.com for j in xrange(num_cpus_per_cluster): 948948Sandreas.hansson@arm.com # 958975Sandreas.hansson@arm.com # First create the Ruby objects associated with this cpu 963738Sstever@eecs.umich.edu # 973738Sstever@eecs.umich.edu l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, 983738Sstever@eecs.umich.edu start_index_bit = block_size_bits, replacement_policy="LRU") 993738Sstever@eecs.umich.edu 1008856Sandreas.hansson@arm.com l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 1019090Sandreas.hansson@arm.com start_index_bit = block_size_bits, replacement_policy="LRU") 1028856Sandreas.hansson@arm.com 1038856Sandreas.hansson@arm.com l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j, 1048856Sandreas.hansson@arm.com Icache = l0i_cache, Dcache = l0d_cache, 10510815Sdavid.guillen@arm.com send_evictions = send_evicts(options), 1068856Sandreas.hansson@arm.com clk_domain=system.cpu[i].clk_domain, 1078856Sandreas.hansson@arm.com ruby_system = ruby_system) 1083738Sstever@eecs.umich.edu 1093738Sstever@eecs.umich.edu cpu_seq = RubySequencer(version = i, icache = l0i_cache, 1108856Sandreas.hansson@arm.com clk_domain=system.cpu[i].clk_domain, 1118914Sandreas.hansson@arm.com dcache = l0d_cache, ruby_system = ruby_system) 1128914Sandreas.hansson@arm.com 1138914Sandreas.hansson@arm.com l0_cntrl.sequencer = cpu_seq 1148914Sandreas.hansson@arm.com 1158914Sandreas.hansson@arm.com l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 11610713Sandreas.hansson@arm.com start_index_bit = block_size_bits, is_icache = False) 1178914Sandreas.hansson@arm.com 1188914Sandreas.hansson@arm.com l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, 1198914Sandreas.hansson@arm.com cache = l1_cache, l2_select_num_bits = l2_bits, 1208914Sandreas.hansson@arm.com cluster_id = i, ruby_system = ruby_system) 12110815Sdavid.guillen@arm.com 12210713Sandreas.hansson@arm.com exec("ruby_system.l0_cntrl%d = l0_cntrl" % ( 1238914Sandreas.hansson@arm.com i*num_cpus_per_cluster+j)) 1248914Sandreas.hansson@arm.com exec("ruby_system.l1_cntrl%d = l1_cntrl" % ( 1258914Sandreas.hansson@arm.com i*num_cpus_per_cluster+j)) 12610815Sdavid.guillen@arm.com 12710713Sandreas.hansson@arm.com # 12810713Sandreas.hansson@arm.com # Add controllers and sequencers to the appropriate lists 12910713Sandreas.hansson@arm.com # 13010713Sandreas.hansson@arm.com cpu_sequencers.append(cpu_seq) 1318914Sandreas.hansson@arm.com l0_cntrl_nodes.append(l0_cntrl) 1328914Sandreas.hansson@arm.com l1_cntrl_nodes.append(l1_cntrl) 1338914Sandreas.hansson@arm.com 1348914Sandreas.hansson@arm.com # Connect the L0 and L1 controllers 1358914Sandreas.hansson@arm.com l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0 1368914Sandreas.hansson@arm.com l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0 1378914Sandreas.hansson@arm.com 1388914Sandreas.hansson@arm.com # Connect the L1 controllers and the network 1398914Sandreas.hansson@arm.com l1_cntrl.requestToL2 = ruby_system.network.slave 1408914Sandreas.hansson@arm.com l1_cntrl.responseToL2 = ruby_system.network.slave 1418914Sandreas.hansson@arm.com l1_cntrl.unblockToL2 = ruby_system.network.slave 1428856Sandreas.hansson@arm.com 1438856Sandreas.hansson@arm.com l1_cntrl.requestFromL2 = ruby_system.network.master 1448856Sandreas.hansson@arm.com l1_cntrl.responseFromL2 = ruby_system.network.master 1458856Sandreas.hansson@arm.com 1463738Sstever@eecs.umich.edu 1478856Sandreas.hansson@arm.com for j in xrange(num_l2caches_per_cluster): 1483738Sstever@eecs.umich.edu l2_cache = L2Cache(size = options.l2_size, 1498914Sandreas.hansson@arm.com assoc = options.l2_assoc, 15010713Sandreas.hansson@arm.com start_index_bit = l2_index_start) 15110713Sandreas.hansson@arm.com 15210713Sandreas.hansson@arm.com l2_cntrl = L2Cache_Controller( 1538914Sandreas.hansson@arm.com version = i * num_l2caches_per_cluster + j, 1548856Sandreas.hansson@arm.com L2cache = l2_cache, cluster_id = i, 15510815Sdavid.guillen@arm.com transitions_per_cycle=options.ports, 1563738Sstever@eecs.umich.edu ruby_system = ruby_system) 1578856Sandreas.hansson@arm.com 1584478Sstever@eecs.umich.edu exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 1598975Sandreas.hansson@arm.com i * num_l2caches_per_cluster + j)) 1608948Sandreas.hansson@arm.com l2_cntrl_nodes.append(l2_cntrl) 1618975Sandreas.hansson@arm.com 1623738Sstever@eecs.umich.edu # Connect the L2 controllers and the network 1638948Sandreas.hansson@arm.com l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave 1643738Sstever@eecs.umich.edu l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 1658948Sandreas.hansson@arm.com l2_cntrl.responseFromL2Cache = ruby_system.network.slave 1664458Sstever@eecs.umich.edu 1678856Sandreas.hansson@arm.com l2_cntrl.unblockToL2Cache = ruby_system.network.master 1688856Sandreas.hansson@arm.com l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 16910815Sdavid.guillen@arm.com l2_cntrl.responseToL2Cache = ruby_system.network.master 1708856Sandreas.hansson@arm.com 1713738Sstever@eecs.umich.edu phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1723738Sstever@eecs.umich.edu assert(phys_mem_size % options.num_dirs == 0) 1732810Srdreslin@umich.edu mem_module_size = phys_mem_size / options.num_dirs 17410815Sdavid.guillen@arm.com 1754626Sstever@eecs.umich.edu # Run each of the ruby memory controllers at a ratio of the frequency of 1762810Srdreslin@umich.edu # the ruby system 1773861Sstever@eecs.umich.edu # clk_divider value is a fix to pass regression. 1782810Srdreslin@umich.edu ruby_system.memctrl_clk_domain = DerivedClockDomain( 1794671Sstever@eecs.umich.edu clk_domain=ruby_system.clk_domain, 18010815Sdavid.guillen@arm.com clk_divider=3) 1814671Sstever@eecs.umich.edu 1822810Srdreslin@umich.edu for i in xrange(options.num_dirs): 1835707Shsul@eecs.umich.edu # 1843860Sstever@eecs.umich.edu # Create the Ruby objects associated with the directory controller 1853860Sstever@eecs.umich.edu # 1863860Sstever@eecs.umich.edu dir_size = MemorySize('0B') 1875875Ssteve.reinhardt@amd.com dir_size.value = mem_module_size 18810345SCurtis.Dunham@arm.com 18910345SCurtis.Dunham@arm.com dir_cntrl = Directory_Controller(version = i, 19010345SCurtis.Dunham@arm.com directory = RubyDirectoryMemory( 19110345SCurtis.Dunham@arm.com version = i, size = dir_size), 19210345SCurtis.Dunham@arm.com transitions_per_cycle = options.ports, 1935875Ssteve.reinhardt@amd.com ruby_system = ruby_system) 1945875Ssteve.reinhardt@amd.com 1955875Ssteve.reinhardt@amd.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1963860Sstever@eecs.umich.edu dir_cntrl_nodes.append(dir_cntrl) 1973860Sstever@eecs.umich.edu 1989063SAli.Saidi@ARM.com # Connect the directory controllers and the network 1999063SAli.Saidi@ARM.com dir_cntrl.requestToDir = ruby_system.network.master 2009063SAli.Saidi@ARM.com dir_cntrl.responseToDir = ruby_system.network.master 2019063SAli.Saidi@ARM.com dir_cntrl.responseFromDir = ruby_system.network.slave 2029063SAli.Saidi@ARM.com 2039063SAli.Saidi@ARM.com for i, dma_port in enumerate(dma_ports): 2049063SAli.Saidi@ARM.com # 2053860Sstever@eecs.umich.edu # Create the Ruby objects associated with the dma controller 2063860Sstever@eecs.umich.edu # 20710048Saminfar@gmail.com dma_seq = DMASequencer(version = i, 2083860Sstever@eecs.umich.edu ruby_system = ruby_system) 2093860Sstever@eecs.umich.edu 2105707Shsul@eecs.umich.edu dma_cntrl = DMA_Controller(version = i, 2113860Sstever@eecs.umich.edu dma_sequencer = dma_seq, 21210815Sdavid.guillen@arm.com transitions_per_cycle = options.ports, 2139288Sandreas.hansson@arm.com ruby_system = ruby_system) 2144219Srdreslin@umich.edu 2154219Srdreslin@umich.edu exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 2164219Srdreslin@umich.edu exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 2174219Srdreslin@umich.edu dma_cntrl_nodes.append(dma_cntrl) 21810815Sdavid.guillen@arm.com 2193860Sstever@eecs.umich.edu # Connect the dma controller to the network 2203860Sstever@eecs.umich.edu dma_cntrl.responseFromDir = ruby_system.network.master 22110028SGiacomo.Gabrielli@arm.com dma_cntrl.requestToDir = ruby_system.network.slave 22210028SGiacomo.Gabrielli@arm.com 22310028SGiacomo.Gabrielli@arm.com all_cntrls = l0_cntrl_nodes + \ 22410028SGiacomo.Gabrielli@arm.com l1_cntrl_nodes + \ 22510028SGiacomo.Gabrielli@arm.com l2_cntrl_nodes + \ 2265350Sstever@gmail.com dir_cntrl_nodes + \ 22710815Sdavid.guillen@arm.com dma_cntrl_nodes 2285350Sstever@gmail.com 2295350Sstever@gmail.com # Create the io controller and the sequencer 2303860Sstever@eecs.umich.edu if full_system: 2313860Sstever@eecs.umich.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 2323860Sstever@eecs.umich.edu ruby_system._io_port = io_seq 2334626Sstever@eecs.umich.edu io_controller = DMA_Controller(version = len(dma_ports), 2343860Sstever@eecs.umich.edu dma_sequencer = io_seq, 2353860Sstever@eecs.umich.edu ruby_system = ruby_system) 2363860Sstever@eecs.umich.edu ruby_system.io_controller = io_controller 2373860Sstever@eecs.umich.edu 23810815Sdavid.guillen@arm.com # Connect the dma controller to the network 2394626Sstever@eecs.umich.edu io_controller.responseFromDir = ruby_system.network.master 2403860Sstever@eecs.umich.edu io_controller.requestToDir = ruby_system.network.slave 2419548Sandreas.hansson@arm.com 2429548Sandreas.hansson@arm.com all_cntrls = all_cntrls + [io_controller] 2439548Sandreas.hansson@arm.com 2449548Sandreas.hansson@arm.com topology = create_topology(all_cntrls, options) 2459548Sandreas.hansson@arm.com return (cpu_sequencers, dir_cntrl_nodes, topology) 2469548Sandreas.hansson@arm.com