MESI_Three_Level.py revision 13731
110008Snilay@cs.wisc.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 211266SBrad.Beckmann@amd.com# Copyright (c) 2009,2015 Advanced Micro Devices, Inc. 310008Snilay@cs.wisc.edu# Copyright (c) 2013 Mark D. Hill and David A. Wood 410008Snilay@cs.wisc.edu# All rights reserved. 510008Snilay@cs.wisc.edu# 610008Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without 710008Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are 810008Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright 910008Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer; 1010008Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright 1110008Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the 1210008Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution; 1310008Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its 1410008Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from 1510008Snilay@cs.wisc.edu# this software without specific prior written permission. 1610008Snilay@cs.wisc.edu# 1710008Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1810008Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1910008Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2010008Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2110008Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2210008Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2310008Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2410008Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2510008Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2610008Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2710008Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2810008Snilay@cs.wisc.edu# 2910008Snilay@cs.wisc.edu# Authors: Brad Beckmann 3010008Snilay@cs.wisc.edu# Nilay Vaish 3110008Snilay@cs.wisc.edu 3210008Snilay@cs.wisc.eduimport math 3310008Snilay@cs.wisc.eduimport m5 3410008Snilay@cs.wisc.edufrom m5.objects import * 3510008Snilay@cs.wisc.edufrom m5.defines import buildEnv 3612065Snikos.nikoleris@arm.comfrom Ruby import create_topology, create_directories 3710529Smorr@cs.wisc.edufrom Ruby import send_evicts 3810008Snilay@cs.wisc.edu 3910008Snilay@cs.wisc.edu# 4011019Sjthestness@gmail.com# Declare caches used by the protocol 4110008Snilay@cs.wisc.edu# 4211019Sjthestness@gmail.comclass L0Cache(RubyCache): pass 4311019Sjthestness@gmail.comclass L1Cache(RubyCache): pass 4411019Sjthestness@gmail.comclass L2Cache(RubyCache): pass 4510008Snilay@cs.wisc.edu 4610008Snilay@cs.wisc.edudef define_options(parser): 4711266SBrad.Beckmann@amd.com parser.add_option("--num-clusters", type = "int", default = 1, 4811266SBrad.Beckmann@amd.com help = "number of clusters in a design in which there are shared\ 4910008Snilay@cs.wisc.edu caches private to clusters") 5010008Snilay@cs.wisc.edu return 5110008Snilay@cs.wisc.edu 5212598Snikos.nikoleris@arm.comdef create_system(options, full_system, system, dma_ports, bootmem, 5312598Snikos.nikoleris@arm.com ruby_system): 5410008Snilay@cs.wisc.edu 5510008Snilay@cs.wisc.edu if buildEnv['PROTOCOL'] != 'MESI_Three_Level': 5611266SBrad.Beckmann@amd.com fatal("This script requires the MESI_Three_Level protocol to be\ 5711266SBrad.Beckmann@amd.com built.") 5810008Snilay@cs.wisc.edu 5910008Snilay@cs.wisc.edu cpu_sequencers = [] 6010008Snilay@cs.wisc.edu 6110008Snilay@cs.wisc.edu # 6210008Snilay@cs.wisc.edu # The ruby network creation expects the list of nodes in the system to be 6311266SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes 6411266SBrad.Beckmann@amd.com # must be listed before the directory nodes and directory nodes before 6511266SBrad.Beckmann@amd.com # dma nodes, etc. 6610008Snilay@cs.wisc.edu # 6710008Snilay@cs.wisc.edu l0_cntrl_nodes = [] 6810008Snilay@cs.wisc.edu l1_cntrl_nodes = [] 6910008Snilay@cs.wisc.edu l2_cntrl_nodes = [] 7010008Snilay@cs.wisc.edu dma_cntrl_nodes = [] 7110008Snilay@cs.wisc.edu 7210008Snilay@cs.wisc.edu assert (options.num_cpus % options.num_clusters == 0) 7310008Snilay@cs.wisc.edu num_cpus_per_cluster = options.num_cpus / options.num_clusters 7410008Snilay@cs.wisc.edu 7510008Snilay@cs.wisc.edu assert (options.num_l2caches % options.num_clusters == 0) 7610008Snilay@cs.wisc.edu num_l2caches_per_cluster = options.num_l2caches / options.num_clusters 7710008Snilay@cs.wisc.edu 7810008Snilay@cs.wisc.edu l2_bits = int(math.log(num_l2caches_per_cluster, 2)) 7910008Snilay@cs.wisc.edu block_size_bits = int(math.log(options.cacheline_size, 2)) 8010008Snilay@cs.wisc.edu l2_index_start = block_size_bits + l2_bits 8110008Snilay@cs.wisc.edu 8210008Snilay@cs.wisc.edu # 8310008Snilay@cs.wisc.edu # Must create the individual controllers before the network to ensure the 8410008Snilay@cs.wisc.edu # controller constructors are called before the network constructor 8510008Snilay@cs.wisc.edu # 8613731Sandreas.sandberg@arm.com for i in range(options.num_clusters): 8713731Sandreas.sandberg@arm.com for j in range(num_cpus_per_cluster): 8810008Snilay@cs.wisc.edu # 8910008Snilay@cs.wisc.edu # First create the Ruby objects associated with this cpu 9010008Snilay@cs.wisc.edu # 9110008Snilay@cs.wisc.edu l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, 9210970Sdavid.hashe@amd.com start_index_bit = block_size_bits, 9310970Sdavid.hashe@amd.com replacement_policy = LRUReplacementPolicy()) 9410008Snilay@cs.wisc.edu 9510008Snilay@cs.wisc.edu l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 9610970Sdavid.hashe@amd.com start_index_bit = block_size_bits, 9710970Sdavid.hashe@amd.com replacement_policy = LRUReplacementPolicy()) 9810008Snilay@cs.wisc.edu 9911266SBrad.Beckmann@amd.com # the ruby random tester reuses num_cpus to specify the 10011266SBrad.Beckmann@amd.com # number of cpu ports connected to the tester object, which 10111266SBrad.Beckmann@amd.com # is stored in system.cpu. because there is only ever one 10211266SBrad.Beckmann@amd.com # tester object, num_cpus is not necessarily equal to the 10311266SBrad.Beckmann@amd.com # size of system.cpu; therefore if len(system.cpu) == 1 10411266SBrad.Beckmann@amd.com # we use system.cpu[0] to set the clk_domain, thereby ensuring 10511266SBrad.Beckmann@amd.com # we don't index off the end of the cpu list. 10611266SBrad.Beckmann@amd.com if len(system.cpu) == 1: 10711266SBrad.Beckmann@amd.com clk_domain = system.cpu[0].clk_domain 10811266SBrad.Beckmann@amd.com else: 10911266SBrad.Beckmann@amd.com clk_domain = system.cpu[i].clk_domain 11011266SBrad.Beckmann@amd.com 11111266SBrad.Beckmann@amd.com l0_cntrl = L0Cache_Controller( 11211266SBrad.Beckmann@amd.com version = i * num_cpus_per_cluster + j, Icache = l0i_cache, 11311266SBrad.Beckmann@amd.com Dcache = l0d_cache, send_evictions = send_evicts(options), 11411266SBrad.Beckmann@amd.com clk_domain = clk_domain, ruby_system = ruby_system) 11510008Snilay@cs.wisc.edu 11610988Snilay@cs.wisc.edu cpu_seq = RubySequencer(version = i * num_cpus_per_cluster + j, 11711266SBrad.Beckmann@amd.com icache = l0i_cache, 11811266SBrad.Beckmann@amd.com clk_domain = clk_domain, 11911266SBrad.Beckmann@amd.com dcache = l0d_cache, 12011266SBrad.Beckmann@amd.com ruby_system = ruby_system) 12110008Snilay@cs.wisc.edu 12210008Snilay@cs.wisc.edu l0_cntrl.sequencer = cpu_seq 12310008Snilay@cs.wisc.edu 12411266SBrad.Beckmann@amd.com l1_cache = L1Cache(size = options.l1d_size, 12511266SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 12611266SBrad.Beckmann@amd.com start_index_bit = block_size_bits, 12711266SBrad.Beckmann@amd.com is_icache = False) 12810008Snilay@cs.wisc.edu 12911266SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller( 13011266SBrad.Beckmann@amd.com version = i * num_cpus_per_cluster + j, 13111266SBrad.Beckmann@amd.com cache = l1_cache, l2_select_num_bits = l2_bits, 13211266SBrad.Beckmann@amd.com cluster_id = i, ruby_system = ruby_system) 13310008Snilay@cs.wisc.edu 13411266SBrad.Beckmann@amd.com exec("ruby_system.l0_cntrl%d = l0_cntrl" 13511266SBrad.Beckmann@amd.com % ( i * num_cpus_per_cluster + j)) 13611266SBrad.Beckmann@amd.com exec("ruby_system.l1_cntrl%d = l1_cntrl" 13711266SBrad.Beckmann@amd.com % ( i * num_cpus_per_cluster + j)) 13810008Snilay@cs.wisc.edu 13910008Snilay@cs.wisc.edu # 14010008Snilay@cs.wisc.edu # Add controllers and sequencers to the appropriate lists 14110008Snilay@cs.wisc.edu # 14210008Snilay@cs.wisc.edu cpu_sequencers.append(cpu_seq) 14310008Snilay@cs.wisc.edu l0_cntrl_nodes.append(l0_cntrl) 14410008Snilay@cs.wisc.edu l1_cntrl_nodes.append(l1_cntrl) 14510311Snilay@cs.wisc.edu 14610311Snilay@cs.wisc.edu # Connect the L0 and L1 controllers 14711022Sjthestness@gmail.com l0_cntrl.mandatoryQueue = MessageBuffer() 14811022Sjthestness@gmail.com l0_cntrl.bufferToL1 = MessageBuffer(ordered = True) 14911022Sjthestness@gmail.com l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1 15011022Sjthestness@gmail.com l0_cntrl.bufferFromL1 = MessageBuffer(ordered = True) 15111022Sjthestness@gmail.com l1_cntrl.bufferToL0 = l0_cntrl.bufferFromL1 15210311Snilay@cs.wisc.edu 15310311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 15411022Sjthestness@gmail.com l1_cntrl.requestToL2 = MessageBuffer() 15511022Sjthestness@gmail.com l1_cntrl.requestToL2.master = ruby_system.network.slave 15611022Sjthestness@gmail.com l1_cntrl.responseToL2 = MessageBuffer() 15711022Sjthestness@gmail.com l1_cntrl.responseToL2.master = ruby_system.network.slave 15811022Sjthestness@gmail.com l1_cntrl.unblockToL2 = MessageBuffer() 15911022Sjthestness@gmail.com l1_cntrl.unblockToL2.master = ruby_system.network.slave 16010311Snilay@cs.wisc.edu 16111022Sjthestness@gmail.com l1_cntrl.requestFromL2 = MessageBuffer() 16211022Sjthestness@gmail.com l1_cntrl.requestFromL2.slave = ruby_system.network.master 16311022Sjthestness@gmail.com l1_cntrl.responseFromL2 = MessageBuffer() 16411022Sjthestness@gmail.com l1_cntrl.responseFromL2.slave = ruby_system.network.master 16510311Snilay@cs.wisc.edu 16610008Snilay@cs.wisc.edu 16713731Sandreas.sandberg@arm.com for j in range(num_l2caches_per_cluster): 16810008Snilay@cs.wisc.edu l2_cache = L2Cache(size = options.l2_size, 16910008Snilay@cs.wisc.edu assoc = options.l2_assoc, 17010008Snilay@cs.wisc.edu start_index_bit = l2_index_start) 17110008Snilay@cs.wisc.edu 17210008Snilay@cs.wisc.edu l2_cntrl = L2Cache_Controller( 17310008Snilay@cs.wisc.edu version = i * num_l2caches_per_cluster + j, 17410008Snilay@cs.wisc.edu L2cache = l2_cache, cluster_id = i, 17511266SBrad.Beckmann@amd.com transitions_per_cycle = options.ports, 17610008Snilay@cs.wisc.edu ruby_system = ruby_system) 17710008Snilay@cs.wisc.edu 17811266SBrad.Beckmann@amd.com exec("ruby_system.l2_cntrl%d = l2_cntrl" 17911266SBrad.Beckmann@amd.com % (i * num_l2caches_per_cluster + j)) 18010008Snilay@cs.wisc.edu l2_cntrl_nodes.append(l2_cntrl) 18110008Snilay@cs.wisc.edu 18210311Snilay@cs.wisc.edu # Connect the L2 controllers and the network 18311022Sjthestness@gmail.com l2_cntrl.DirRequestFromL2Cache = MessageBuffer() 18411022Sjthestness@gmail.com l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave 18511022Sjthestness@gmail.com l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 18611022Sjthestness@gmail.com l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 18711022Sjthestness@gmail.com l2_cntrl.responseFromL2Cache = MessageBuffer() 18811022Sjthestness@gmail.com l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 18910311Snilay@cs.wisc.edu 19011022Sjthestness@gmail.com l2_cntrl.unblockToL2Cache = MessageBuffer() 19111022Sjthestness@gmail.com l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master 19211022Sjthestness@gmail.com l2_cntrl.L1RequestToL2Cache = MessageBuffer() 19311022Sjthestness@gmail.com l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 19411022Sjthestness@gmail.com l2_cntrl.responseToL2Cache = MessageBuffer() 19511022Sjthestness@gmail.com l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 19610311Snilay@cs.wisc.edu 19710008Snilay@cs.wisc.edu # Run each of the ruby memory controllers at a ratio of the frequency of 19810008Snilay@cs.wisc.edu # the ruby system 19910008Snilay@cs.wisc.edu # clk_divider value is a fix to pass regression. 20010008Snilay@cs.wisc.edu ruby_system.memctrl_clk_domain = DerivedClockDomain( 20111266SBrad.Beckmann@amd.com clk_domain = ruby_system.clk_domain, clk_divider = 3) 20210008Snilay@cs.wisc.edu 20312598Snikos.nikoleris@arm.com mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( 20412976Snikos.nikoleris@arm.com options, bootmem, ruby_system, system) 20512598Snikos.nikoleris@arm.com dir_cntrl_nodes = mem_dir_cntrl_nodes[:] 20612598Snikos.nikoleris@arm.com if rom_dir_cntrl_node is not None: 20712598Snikos.nikoleris@arm.com dir_cntrl_nodes.append(rom_dir_cntrl_node) 20812065Snikos.nikoleris@arm.com for dir_cntrl in dir_cntrl_nodes: 20910311Snilay@cs.wisc.edu # Connect the directory controllers and the network 21011022Sjthestness@gmail.com dir_cntrl.requestToDir = MessageBuffer() 21111022Sjthestness@gmail.com dir_cntrl.requestToDir.slave = ruby_system.network.master 21211022Sjthestness@gmail.com dir_cntrl.responseToDir = MessageBuffer() 21311022Sjthestness@gmail.com dir_cntrl.responseToDir.slave = ruby_system.network.master 21411022Sjthestness@gmail.com dir_cntrl.responseFromDir = MessageBuffer() 21511022Sjthestness@gmail.com dir_cntrl.responseFromDir.master = ruby_system.network.slave 21611022Sjthestness@gmail.com dir_cntrl.responseFromMemory = MessageBuffer() 21710311Snilay@cs.wisc.edu 21810008Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 21910008Snilay@cs.wisc.edu # 22010008Snilay@cs.wisc.edu # Create the Ruby objects associated with the dma controller 22110008Snilay@cs.wisc.edu # 22211266SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, ruby_system = ruby_system) 22310008Snilay@cs.wisc.edu 22410008Snilay@cs.wisc.edu dma_cntrl = DMA_Controller(version = i, 22510008Snilay@cs.wisc.edu dma_sequencer = dma_seq, 22610008Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 22710008Snilay@cs.wisc.edu ruby_system = ruby_system) 22810008Snilay@cs.wisc.edu 22910008Snilay@cs.wisc.edu exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 23010008Snilay@cs.wisc.edu exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 23110008Snilay@cs.wisc.edu dma_cntrl_nodes.append(dma_cntrl) 23210008Snilay@cs.wisc.edu 23310652Smalek.musleh@gmail.com # Connect the dma controller to the network 23411022Sjthestness@gmail.com dma_cntrl.mandatoryQueue = MessageBuffer() 23511022Sjthestness@gmail.com dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 23611022Sjthestness@gmail.com dma_cntrl.responseFromDir.slave = ruby_system.network.master 23711022Sjthestness@gmail.com dma_cntrl.requestToDir = MessageBuffer() 23811022Sjthestness@gmail.com dma_cntrl.requestToDir.master = ruby_system.network.slave 23910652Smalek.musleh@gmail.com 24010008Snilay@cs.wisc.edu all_cntrls = l0_cntrl_nodes + \ 24110008Snilay@cs.wisc.edu l1_cntrl_nodes + \ 24210008Snilay@cs.wisc.edu l2_cntrl_nodes + \ 24310008Snilay@cs.wisc.edu dir_cntrl_nodes + \ 24410008Snilay@cs.wisc.edu dma_cntrl_nodes 24510008Snilay@cs.wisc.edu 24610519Snilay@cs.wisc.edu # Create the io controller and the sequencer 24710519Snilay@cs.wisc.edu if full_system: 24810519Snilay@cs.wisc.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 24910519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 25010519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 25110519Snilay@cs.wisc.edu dma_sequencer = io_seq, 25210519Snilay@cs.wisc.edu ruby_system = ruby_system) 25310519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 25410519Snilay@cs.wisc.edu 25510519Snilay@cs.wisc.edu # Connect the dma controller to the network 25611022Sjthestness@gmail.com io_controller.mandatoryQueue = MessageBuffer() 25711022Sjthestness@gmail.com io_controller.responseFromDir = MessageBuffer(ordered = True) 25811022Sjthestness@gmail.com io_controller.responseFromDir.slave = ruby_system.network.master 25911022Sjthestness@gmail.com io_controller.requestToDir = MessageBuffer() 26011022Sjthestness@gmail.com io_controller.requestToDir.master = ruby_system.network.slave 26110519Snilay@cs.wisc.edu 26210519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 26310519Snilay@cs.wisc.edu 26411065Snilay@cs.wisc.edu ruby_system.network.number_of_virtual_networks = 3 26510008Snilay@cs.wisc.edu topology = create_topology(all_cntrls, options) 26612598Snikos.nikoleris@arm.com return (cpu_sequencers, mem_dir_cntrl_nodes, topology) 267