MESI_Three_Level.py revision 11022
12810SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 210941Sdavid.guillen@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 39347SAndreas.Sandberg@arm.com# Copyright (c) 2013 Mark D. Hill and David A. Wood 49347SAndreas.Sandberg@arm.com# All rights reserved. 59347SAndreas.Sandberg@arm.com# 69347SAndreas.Sandberg@arm.com# Redistribution and use in source and binary forms, with or without 79347SAndreas.Sandberg@arm.com# modification, are permitted provided that the following conditions are 89347SAndreas.Sandberg@arm.com# met: redistributions of source code must retain the above copyright 99347SAndreas.Sandberg@arm.com# notice, this list of conditions and the following disclaimer; 109347SAndreas.Sandberg@arm.com# redistributions in binary form must reproduce the above copyright 119347SAndreas.Sandberg@arm.com# notice, this list of conditions and the following disclaimer in the 129347SAndreas.Sandberg@arm.com# documentation and/or other materials provided with the distribution; 139347SAndreas.Sandberg@arm.com# neither the name of the copyright holders nor the names of its 142810SN/A# contributors may be used to endorse or promote products derived from 152810SN/A# this software without specific prior written permission. 162810SN/A# 172810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212810SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222810SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232810SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242810SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262810SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282810SN/A# 292810SN/A# Authors: Brad Beckmann 302810SN/A# Nilay Vaish 312810SN/A 322810SN/Aimport math 332810SN/Aimport m5 342810SN/Afrom m5.objects import * 352810SN/Afrom m5.defines import buildEnv 362810SN/Afrom Ruby import create_topology 372810SN/Afrom Ruby import send_evicts 382810SN/A 392810SN/A# 402810SN/A# Declare caches used by the protocol 412810SN/A# 422810SN/Aclass L0Cache(RubyCache): pass 432810SN/Aclass L1Cache(RubyCache): pass 442810SN/Aclass L2Cache(RubyCache): pass 452810SN/A 462810SN/Adef define_options(parser): 472810SN/A parser.add_option("--num-clusters", type="int", default=1, 482810SN/A help="number of clusters in a design in which there are shared\ 492810SN/A caches private to clusters") 502810SN/A return 512810SN/A 522810SN/Adef create_system(options, full_system, system, dma_ports, ruby_system): 538229Snate@binkert.org 548229Snate@binkert.org if buildEnv['PROTOCOL'] != 'MESI_Three_Level': 552810SN/A fatal("This script requires the MESI_Three_Level protocol to be built.") 5610815Sdavid.guillen@arm.com 579796Sprakash.ramrakhyani@arm.com cpu_sequencers = [] 589796Sprakash.ramrakhyani@arm.com 592810SN/A # 602810SN/A # The ruby network creation expects the list of nodes in the system to be 612810SN/A # consistent with the NetDest list. Therefore the l1 controller nodes must be 622810SN/A # listed before the directory nodes and directory nodes before dma nodes, etc. 632810SN/A # 642810SN/A l0_cntrl_nodes = [] 659796Sprakash.ramrakhyani@arm.com l1_cntrl_nodes = [] 662810SN/A l2_cntrl_nodes = [] 672810SN/A dir_cntrl_nodes = [] 689796Sprakash.ramrakhyani@arm.com dma_cntrl_nodes = [] 699796Sprakash.ramrakhyani@arm.com 709796Sprakash.ramrakhyani@arm.com assert (options.num_cpus % options.num_clusters == 0) 719796Sprakash.ramrakhyani@arm.com num_cpus_per_cluster = options.num_cpus / options.num_clusters 7211722Ssophiane.senni@gmail.com 7311722Ssophiane.senni@gmail.com assert (options.num_l2caches % options.num_clusters == 0) 7411722Ssophiane.senni@gmail.com num_l2caches_per_cluster = options.num_l2caches / options.num_clusters 7511722Ssophiane.senni@gmail.com 7611722Ssophiane.senni@gmail.com l2_bits = int(math.log(num_l2caches_per_cluster, 2)) 7711722Ssophiane.senni@gmail.com block_size_bits = int(math.log(options.cacheline_size, 2)) 7811722Ssophiane.senni@gmail.com l2_index_start = block_size_bits + l2_bits 7910693SMarco.Balboni@ARM.com 802810SN/A # 812810SN/A # Must create the individual controllers before the network to ensure the 822810SN/A # controller constructors are called before the network constructor 832810SN/A # 842810SN/A for i in xrange(options.num_clusters): 852810SN/A for j in xrange(num_cpus_per_cluster): 862810SN/A # 872810SN/A # First create the Ruby objects associated with this cpu 882810SN/A # 892810SN/A l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, 902810SN/A start_index_bit = block_size_bits, 916978SLisa.Hsu@amd.com replacement_policy = LRUReplacementPolicy()) 926978SLisa.Hsu@amd.com 936978SLisa.Hsu@amd.com l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 942810SN/A start_index_bit = block_size_bits, 952810SN/A replacement_policy = LRUReplacementPolicy()) 962810SN/A 972810SN/A l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j, 982810SN/A Icache = l0i_cache, Dcache = l0d_cache, 992810SN/A send_evictions = send_evicts(options), 1002810SN/A clk_domain=system.cpu[i].clk_domain, 1015999Snate@binkert.org ruby_system = ruby_system) 1022810SN/A 1035999Snate@binkert.org cpu_seq = RubySequencer(version = i * num_cpus_per_cluster + j, 1042810SN/A icache = l0i_cache, 1052810SN/A clk_domain=system.cpu[i].clk_domain, 1065999Snate@binkert.org dcache = l0d_cache, ruby_system = ruby_system) 1072810SN/A 1082810SN/A l0_cntrl.sequencer = cpu_seq 1092810SN/A 1102810SN/A l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 1112810SN/A start_index_bit = block_size_bits, is_icache = False) 1122810SN/A 1135999Snate@binkert.org l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, 1142810SN/A cache = l1_cache, l2_select_num_bits = l2_bits, 1152810SN/A cluster_id = i, ruby_system = ruby_system) 1162810SN/A 1172810SN/A exec("ruby_system.l0_cntrl%d = l0_cntrl" % ( 1182810SN/A i*num_cpus_per_cluster+j)) 1192810SN/A exec("ruby_system.l1_cntrl%d = l1_cntrl" % ( 1202810SN/A i*num_cpus_per_cluster+j)) 1212810SN/A 1225999Snate@binkert.org # 1236978SLisa.Hsu@amd.com # Add controllers and sequencers to the appropriate lists 1248833Sdam.sunwoo@arm.com # 1256978SLisa.Hsu@amd.com cpu_sequencers.append(cpu_seq) 1266978SLisa.Hsu@amd.com l0_cntrl_nodes.append(l0_cntrl) 1278833Sdam.sunwoo@arm.com l1_cntrl_nodes.append(l1_cntrl) 1286978SLisa.Hsu@amd.com 1296978SLisa.Hsu@amd.com # Connect the L0 and L1 controllers 13010024Sdam.sunwoo@arm.com l0_cntrl.mandatoryQueue = MessageBuffer() 13110024Sdam.sunwoo@arm.com l0_cntrl.bufferToL1 = MessageBuffer(ordered = True) 13210024Sdam.sunwoo@arm.com l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1 13310024Sdam.sunwoo@arm.com l0_cntrl.bufferFromL1 = MessageBuffer(ordered = True) 13410024Sdam.sunwoo@arm.com l1_cntrl.bufferToL0 = l0_cntrl.bufferFromL1 13510024Sdam.sunwoo@arm.com 13610024Sdam.sunwoo@arm.com # Connect the L1 controllers and the network 13710024Sdam.sunwoo@arm.com l1_cntrl.requestToL2 = MessageBuffer() 13810024Sdam.sunwoo@arm.com l1_cntrl.requestToL2.master = ruby_system.network.slave 13910025Stimothy.jones@arm.com l1_cntrl.responseToL2 = MessageBuffer() 14010025Stimothy.jones@arm.com l1_cntrl.responseToL2.master = ruby_system.network.slave 14110025Stimothy.jones@arm.com l1_cntrl.unblockToL2 = MessageBuffer() 14210025Stimothy.jones@arm.com l1_cntrl.unblockToL2.master = ruby_system.network.slave 14310025Stimothy.jones@arm.com 1442810SN/A l1_cntrl.requestFromL2 = MessageBuffer() 1452810SN/A l1_cntrl.requestFromL2.slave = ruby_system.network.master 1462810SN/A l1_cntrl.responseFromL2 = MessageBuffer() 1472810SN/A l1_cntrl.responseFromL2.slave = ruby_system.network.master 1482810SN/A 1499796Sprakash.ramrakhyani@arm.com 1509796Sprakash.ramrakhyani@arm.com for j in xrange(num_l2caches_per_cluster): 1512810SN/A l2_cache = L2Cache(size = options.l2_size, 1522810SN/A assoc = options.l2_assoc, 1532810SN/A start_index_bit = l2_index_start) 1542810SN/A 1552810SN/A l2_cntrl = L2Cache_Controller( 1562810SN/A version = i * num_l2caches_per_cluster + j, 1572810SN/A L2cache = l2_cache, cluster_id = i, 1589796Sprakash.ramrakhyani@arm.com transitions_per_cycle=options.ports, 1592810SN/A ruby_system = ruby_system) 1602810SN/A 1612810SN/A exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 1622810SN/A i * num_l2caches_per_cluster + j)) 1632810SN/A l2_cntrl_nodes.append(l2_cntrl) 1649796Sprakash.ramrakhyani@arm.com 1652810SN/A # Connect the L2 controllers and the network 1669796Sprakash.ramrakhyani@arm.com l2_cntrl.DirRequestFromL2Cache = MessageBuffer() 1672810SN/A l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave 1682810SN/A l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 1692810SN/A l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 1702810SN/A l2_cntrl.responseFromL2Cache = MessageBuffer() 1712810SN/A l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 1722810SN/A 1737612SGene.Wu@arm.com l2_cntrl.unblockToL2Cache = MessageBuffer() 1747612SGene.Wu@arm.com l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master 17510024Sdam.sunwoo@arm.com l2_cntrl.L1RequestToL2Cache = MessageBuffer() 17610024Sdam.sunwoo@arm.com l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 17710024Sdam.sunwoo@arm.com l2_cntrl.responseToL2Cache = MessageBuffer() 17810024Sdam.sunwoo@arm.com l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 17910024Sdam.sunwoo@arm.com 1809663Suri.wiener@arm.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1819663Suri.wiener@arm.com assert(phys_mem_size % options.num_dirs == 0) 1829663Suri.wiener@arm.com mem_module_size = phys_mem_size / options.num_dirs 18310815Sdavid.guillen@arm.com 18410815Sdavid.guillen@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 18510815Sdavid.guillen@arm.com # the ruby system 18610815Sdavid.guillen@arm.com # clk_divider value is a fix to pass regression. 18710815Sdavid.guillen@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 18810815Sdavid.guillen@arm.com clk_domain=ruby_system.clk_domain, 18910815Sdavid.guillen@arm.com clk_divider=3) 19010815Sdavid.guillen@arm.com 19110815Sdavid.guillen@arm.com for i in xrange(options.num_dirs): 19210815Sdavid.guillen@arm.com # 19310815Sdavid.guillen@arm.com # Create the Ruby objects associated with the directory controller 19410815Sdavid.guillen@arm.com # 19510815Sdavid.guillen@arm.com dir_size = MemorySize('0B') 19610815Sdavid.guillen@arm.com dir_size.value = mem_module_size 19710815Sdavid.guillen@arm.com 19810815Sdavid.guillen@arm.com dir_cntrl = Directory_Controller(version = i, 19910941Sdavid.guillen@arm.com directory = RubyDirectoryMemory( 20010941Sdavid.guillen@arm.com version = i, size = dir_size), 20110941Sdavid.guillen@arm.com transitions_per_cycle = options.ports, 20210941Sdavid.guillen@arm.com ruby_system = ruby_system) 20310941Sdavid.guillen@arm.com 20410941Sdavid.guillen@arm.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 20510941Sdavid.guillen@arm.com dir_cntrl_nodes.append(dir_cntrl) 20610941Sdavid.guillen@arm.com 20710941Sdavid.guillen@arm.com # Connect the directory controllers and the network 20810941Sdavid.guillen@arm.com dir_cntrl.requestToDir = MessageBuffer() 20910941Sdavid.guillen@arm.com dir_cntrl.requestToDir.slave = ruby_system.network.master 21010941Sdavid.guillen@arm.com dir_cntrl.responseToDir = MessageBuffer() 21110941Sdavid.guillen@arm.com dir_cntrl.responseToDir.slave = ruby_system.network.master 21210941Sdavid.guillen@arm.com dir_cntrl.responseFromDir = MessageBuffer() 21310941Sdavid.guillen@arm.com dir_cntrl.responseFromDir.master = ruby_system.network.slave 21410941Sdavid.guillen@arm.com dir_cntrl.responseFromMemory = MessageBuffer() 21510941Sdavid.guillen@arm.com 21610941Sdavid.guillen@arm.com for i, dma_port in enumerate(dma_ports): 21710941Sdavid.guillen@arm.com # 21810941Sdavid.guillen@arm.com # Create the Ruby objects associated with the dma controller 21910941Sdavid.guillen@arm.com # 22010941Sdavid.guillen@arm.com dma_seq = DMASequencer(version = i, 22110941Sdavid.guillen@arm.com ruby_system = ruby_system) 22210941Sdavid.guillen@arm.com 22310941Sdavid.guillen@arm.com dma_cntrl = DMA_Controller(version = i, 22410941Sdavid.guillen@arm.com dma_sequencer = dma_seq, 22510941Sdavid.guillen@arm.com transitions_per_cycle = options.ports, 22610941Sdavid.guillen@arm.com ruby_system = ruby_system) 22710941Sdavid.guillen@arm.com 22810941Sdavid.guillen@arm.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 22910941Sdavid.guillen@arm.com exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 23010815Sdavid.guillen@arm.com dma_cntrl_nodes.append(dma_cntrl) 23110815Sdavid.guillen@arm.com 23210815Sdavid.guillen@arm.com # Connect the dma controller to the network 23310815Sdavid.guillen@arm.com dma_cntrl.mandatoryQueue = MessageBuffer() 23410815Sdavid.guillen@arm.com dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 23510815Sdavid.guillen@arm.com dma_cntrl.responseFromDir.slave = ruby_system.network.master 23610815Sdavid.guillen@arm.com dma_cntrl.requestToDir = MessageBuffer() 23710815Sdavid.guillen@arm.com dma_cntrl.requestToDir.master = ruby_system.network.slave 23810815Sdavid.guillen@arm.com 23910815Sdavid.guillen@arm.com all_cntrls = l0_cntrl_nodes + \ 24010815Sdavid.guillen@arm.com l1_cntrl_nodes + \ 24110815Sdavid.guillen@arm.com l2_cntrl_nodes + \ 24210815Sdavid.guillen@arm.com dir_cntrl_nodes + \ 24310815Sdavid.guillen@arm.com dma_cntrl_nodes 24410815Sdavid.guillen@arm.com 24510815Sdavid.guillen@arm.com # Create the io controller and the sequencer 2462810SN/A if full_system: 2472810SN/A io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 2482810SN/A ruby_system._io_port = io_seq 2492810SN/A io_controller = DMA_Controller(version = len(dma_ports), 2502810SN/A dma_sequencer = io_seq, 2512810SN/A ruby_system = ruby_system) 2522810SN/A ruby_system.io_controller = io_controller 2532810SN/A 2542810SN/A # Connect the dma controller to the network 2552810SN/A io_controller.mandatoryQueue = MessageBuffer() 25610024Sdam.sunwoo@arm.com io_controller.responseFromDir = MessageBuffer(ordered = True) 25710024Sdam.sunwoo@arm.com io_controller.responseFromDir.slave = ruby_system.network.master 25810024Sdam.sunwoo@arm.com io_controller.requestToDir = MessageBuffer() 25910024Sdam.sunwoo@arm.com io_controller.requestToDir.master = ruby_system.network.slave 26010024Sdam.sunwoo@arm.com 26110024Sdam.sunwoo@arm.com all_cntrls = all_cntrls + [io_controller] 26210024Sdam.sunwoo@arm.com 26310024Sdam.sunwoo@arm.com topology = create_topology(all_cntrls, options) 2642810SN/A return (cpu_sequencers, dir_cntrl_nodes, topology) 265