MESI_Three_Level.py revision 10652
1278SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 22188SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 3278SN/A# Copyright (c) 2013 Mark D. Hill and David A. Wood 4278SN/A# All rights reserved. 5278SN/A# 6278SN/A# Redistribution and use in source and binary forms, with or without 7278SN/A# modification, are permitted provided that the following conditions are 8278SN/A# met: redistributions of source code must retain the above copyright 9278SN/A# notice, this list of conditions and the following disclaimer; 10278SN/A# redistributions in binary form must reproduce the above copyright 11278SN/A# notice, this list of conditions and the following disclaimer in the 12278SN/A# documentation and/or other materials provided with the distribution; 13278SN/A# neither the name of the copyright holders nor the names of its 14278SN/A# contributors may be used to endorse or promote products derived from 15278SN/A# this software without specific prior written permission. 16278SN/A# 17278SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18278SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19278SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20278SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21278SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22278SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23278SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24278SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25278SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26278SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665SN/A# 292665SN/A# Authors: Brad Beckmann 30278SN/A# Nilay Vaish 31278SN/A 32275SN/Aimport math 33287SN/Aimport m5 3412157Sandreas.sandberg@arm.comfrom m5.objects import * 352188SN/Afrom m5.defines import buildEnv 36275SN/Afrom Ruby import create_topology 372188SN/Afrom Ruby import send_evicts 382188SN/A 392188SN/A# 402188SN/A# Note: the L1 Cache latency is only used by the sequencer on fast path hits 412188SN/A# 422188SN/Aclass L0Cache(RubyCache): 432188SN/A latency = 1 442188SN/A 452188SN/Aclass L1Cache(RubyCache): 462188SN/A latency = 5 472188SN/A 482188SN/A# 492188SN/A# Note: the L2 Cache latency is not currently used 502188SN/A# 515543Ssaidi@eecs.umich.educlass L2Cache(RubyCache): 525543Ssaidi@eecs.umich.edu latency = 15 535543Ssaidi@eecs.umich.edu 545543Ssaidi@eecs.umich.edudef define_options(parser): 555505Snate@binkert.org parser.add_option("--num-clusters", type="int", default=1, 565505Snate@binkert.org help="number of clusters in a design in which there are shared\ 5712157Sandreas.sandberg@arm.com caches private to clusters") 5812157Sandreas.sandberg@arm.com return 5912157Sandreas.sandberg@arm.com 6012157Sandreas.sandberg@arm.comdef create_system(options, full_system, system, dma_ports, ruby_system): 6112157Sandreas.sandberg@arm.com 6212157Sandreas.sandberg@arm.com if buildEnv['PROTOCOL'] != 'MESI_Three_Level': 6312157Sandreas.sandberg@arm.com fatal("This script requires the MESI_Three_Level protocol to be built.") 6412157Sandreas.sandberg@arm.com 6512157Sandreas.sandberg@arm.com cpu_sequencers = [] 6612157Sandreas.sandberg@arm.com 6712157Sandreas.sandberg@arm.com # 6812157Sandreas.sandberg@arm.com # The ruby network creation expects the list of nodes in the system to be 6912157Sandreas.sandberg@arm.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 7012157Sandreas.sandberg@arm.com # listed before the directory nodes and directory nodes before dma nodes, etc. 7112157Sandreas.sandberg@arm.com # 7212157Sandreas.sandberg@arm.com l0_cntrl_nodes = [] 7312157Sandreas.sandberg@arm.com l1_cntrl_nodes = [] 7412157Sandreas.sandberg@arm.com l2_cntrl_nodes = [] 7512157Sandreas.sandberg@arm.com dir_cntrl_nodes = [] 76275SN/A dma_cntrl_nodes = [] 7712157Sandreas.sandberg@arm.com 7812157Sandreas.sandberg@arm.com assert (options.num_cpus % options.num_clusters == 0) 7912157Sandreas.sandberg@arm.com num_cpus_per_cluster = options.num_cpus / options.num_clusters 8012157Sandreas.sandberg@arm.com 8112157Sandreas.sandberg@arm.com assert (options.num_l2caches % options.num_clusters == 0) 8212157Sandreas.sandberg@arm.com num_l2caches_per_cluster = options.num_l2caches / options.num_clusters 8312157Sandreas.sandberg@arm.com 8412157Sandreas.sandberg@arm.com l2_bits = int(math.log(num_l2caches_per_cluster, 2)) 8512157Sandreas.sandberg@arm.com block_size_bits = int(math.log(options.cacheline_size, 2)) 8612157Sandreas.sandberg@arm.com l2_index_start = block_size_bits + l2_bits 8712157Sandreas.sandberg@arm.com 8812157Sandreas.sandberg@arm.com # 8912157Sandreas.sandberg@arm.com # Must create the individual controllers before the network to ensure the 9012157Sandreas.sandberg@arm.com # controller constructors are called before the network constructor 9112157Sandreas.sandberg@arm.com # 9212157Sandreas.sandberg@arm.com for i in xrange(options.num_clusters): 935951Ssaidi@eecs.umich.edu for j in xrange(num_cpus_per_cluster): 945951Ssaidi@eecs.umich.edu # 952188SN/A # First create the Ruby objects associated with this cpu 96275SN/A # 9712160Sandreas.sandberg@arm.com l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, 9812160Sandreas.sandberg@arm.com start_index_bit = block_size_bits, replacement_policy="LRU") 9912160Sandreas.sandberg@arm.com 10012160Sandreas.sandberg@arm.com l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 10112160Sandreas.sandberg@arm.com start_index_bit = block_size_bits, replacement_policy="LRU") 10212160Sandreas.sandberg@arm.com 10312160Sandreas.sandberg@arm.com l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j, 1045505Snate@binkert.org Icache = l0i_cache, Dcache = l0d_cache, 10512160Sandreas.sandberg@arm.com send_evictions = send_evicts(options), 10612160Sandreas.sandberg@arm.com clk_domain=system.cpu[i].clk_domain, 1075505Snate@binkert.org ruby_system = ruby_system) 1085505Snate@binkert.org 10912160Sandreas.sandberg@arm.com cpu_seq = RubySequencer(version = i, icache = l0i_cache, 1105505Snate@binkert.org clk_domain=system.cpu[i].clk_domain, 11112160Sandreas.sandberg@arm.com dcache = l0d_cache, ruby_system = ruby_system) 11212160Sandreas.sandberg@arm.com 11312160Sandreas.sandberg@arm.com l0_cntrl.sequencer = cpu_seq 11412160Sandreas.sandberg@arm.com 1155505Snate@binkert.org l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 116275SN/A start_index_bit = block_size_bits, is_icache = False) 1175951Ssaidi@eecs.umich.edu 1185951Ssaidi@eecs.umich.edu l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, 1195951Ssaidi@eecs.umich.edu cache = l1_cache, l2_select_num_bits = l2_bits, 1205951Ssaidi@eecs.umich.edu cluster_id = i, ruby_system = ruby_system) 1215951Ssaidi@eecs.umich.edu 1225951Ssaidi@eecs.umich.edu exec("ruby_system.l0_cntrl%d = l0_cntrl" % ( 1235951Ssaidi@eecs.umich.edu i*num_cpus_per_cluster+j)) 1245951Ssaidi@eecs.umich.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % ( 1255951Ssaidi@eecs.umich.edu i*num_cpus_per_cluster+j)) 1265951Ssaidi@eecs.umich.edu 1275951Ssaidi@eecs.umich.edu # 1285951Ssaidi@eecs.umich.edu # Add controllers and sequencers to the appropriate lists 1295951Ssaidi@eecs.umich.edu # 1305951Ssaidi@eecs.umich.edu cpu_sequencers.append(cpu_seq) 1315951Ssaidi@eecs.umich.edu l0_cntrl_nodes.append(l0_cntrl) 1325951Ssaidi@eecs.umich.edu l1_cntrl_nodes.append(l1_cntrl) 1335951Ssaidi@eecs.umich.edu 134 # Connect the L0 and L1 controllers 135 l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0 136 l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0 137 138 # Connect the L1 controllers and the network 139 l1_cntrl.requestToL2 = ruby_system.network.slave 140 l1_cntrl.responseToL2 = ruby_system.network.slave 141 l1_cntrl.unblockToL2 = ruby_system.network.slave 142 143 l1_cntrl.requestFromL2 = ruby_system.network.master 144 l1_cntrl.responseFromL2 = ruby_system.network.master 145 146 147 for j in xrange(num_l2caches_per_cluster): 148 l2_cache = L2Cache(size = options.l2_size, 149 assoc = options.l2_assoc, 150 start_index_bit = l2_index_start) 151 152 l2_cntrl = L2Cache_Controller( 153 version = i * num_l2caches_per_cluster + j, 154 L2cache = l2_cache, cluster_id = i, 155 transitions_per_cycle=options.ports, 156 ruby_system = ruby_system) 157 158 exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 159 i * num_l2caches_per_cluster + j)) 160 l2_cntrl_nodes.append(l2_cntrl) 161 162 # Connect the L2 controllers and the network 163 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave 164 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 165 l2_cntrl.responseFromL2Cache = ruby_system.network.slave 166 167 l2_cntrl.unblockToL2Cache = ruby_system.network.master 168 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 169 l2_cntrl.responseToL2Cache = ruby_system.network.master 170 171 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 172 assert(phys_mem_size % options.num_dirs == 0) 173 mem_module_size = phys_mem_size / options.num_dirs 174 175 # Run each of the ruby memory controllers at a ratio of the frequency of 176 # the ruby system 177 # clk_divider value is a fix to pass regression. 178 ruby_system.memctrl_clk_domain = DerivedClockDomain( 179 clk_domain=ruby_system.clk_domain, 180 clk_divider=3) 181 182 for i in xrange(options.num_dirs): 183 # 184 # Create the Ruby objects associated with the directory controller 185 # 186 dir_size = MemorySize('0B') 187 dir_size.value = mem_module_size 188 189 dir_cntrl = Directory_Controller(version = i, 190 directory = RubyDirectoryMemory( 191 version = i, size = dir_size), 192 transitions_per_cycle = options.ports, 193 ruby_system = ruby_system) 194 195 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 196 dir_cntrl_nodes.append(dir_cntrl) 197 198 # Connect the directory controllers and the network 199 dir_cntrl.requestToDir = ruby_system.network.master 200 dir_cntrl.responseToDir = ruby_system.network.master 201 dir_cntrl.responseFromDir = ruby_system.network.slave 202 203 for i, dma_port in enumerate(dma_ports): 204 # 205 # Create the Ruby objects associated with the dma controller 206 # 207 dma_seq = DMASequencer(version = i, 208 ruby_system = ruby_system) 209 210 dma_cntrl = DMA_Controller(version = i, 211 dma_sequencer = dma_seq, 212 transitions_per_cycle = options.ports, 213 ruby_system = ruby_system) 214 215 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 216 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 217 dma_cntrl_nodes.append(dma_cntrl) 218 219 # Connect the dma controller to the network 220 dma_cntrl.responseFromDir = ruby_system.network.master 221 dma_cntrl.requestToDir = ruby_system.network.slave 222 223 all_cntrls = l0_cntrl_nodes + \ 224 l1_cntrl_nodes + \ 225 l2_cntrl_nodes + \ 226 dir_cntrl_nodes + \ 227 dma_cntrl_nodes 228 229 # Create the io controller and the sequencer 230 if full_system: 231 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 232 ruby_system._io_port = io_seq 233 io_controller = DMA_Controller(version = len(dma_ports), 234 dma_sequencer = io_seq, 235 ruby_system = ruby_system) 236 ruby_system.io_controller = io_controller 237 238 # Connect the dma controller to the network 239 io_controller.responseFromDir = ruby_system.network.master 240 io_controller.requestToDir = ruby_system.network.slave 241 242 all_cntrls = all_cntrls + [io_controller] 243 244 topology = create_topology(all_cntrls, options) 245 return (cpu_sequencers, dir_cntrl_nodes, topology) 246