MESI_Three_Level.py revision 10116
110008Snilay@cs.wisc.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 210008Snilay@cs.wisc.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 310008Snilay@cs.wisc.edu# Copyright (c) 2013 Mark D. Hill and David A. Wood 410008Snilay@cs.wisc.edu# All rights reserved. 510008Snilay@cs.wisc.edu# 610008Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without 710008Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are 810008Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright 910008Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer; 1010008Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright 1110008Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the 1210008Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution; 1310008Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its 1410008Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from 1510008Snilay@cs.wisc.edu# this software without specific prior written permission. 1610008Snilay@cs.wisc.edu# 1710008Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1810008Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1910008Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2010008Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2110008Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2210008Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2310008Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2410008Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2510008Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2610008Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2710008Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2810008Snilay@cs.wisc.edu# 2910008Snilay@cs.wisc.edu# Authors: Brad Beckmann 3010008Snilay@cs.wisc.edu# Nilay Vaish 3110008Snilay@cs.wisc.edu 3210008Snilay@cs.wisc.eduimport math 3310008Snilay@cs.wisc.eduimport m5 3410008Snilay@cs.wisc.edufrom m5.objects import * 3510008Snilay@cs.wisc.edufrom m5.defines import buildEnv 3610008Snilay@cs.wisc.edufrom Ruby import create_topology 3710008Snilay@cs.wisc.edu 3810008Snilay@cs.wisc.edu# 3910008Snilay@cs.wisc.edu# Note: the L1 Cache latency is only used by the sequencer on fast path hits 4010008Snilay@cs.wisc.edu# 4110008Snilay@cs.wisc.educlass L0Cache(RubyCache): 4210008Snilay@cs.wisc.edu latency = 1 4310008Snilay@cs.wisc.edu 4410008Snilay@cs.wisc.educlass L1Cache(RubyCache): 4510008Snilay@cs.wisc.edu latency = 5 4610008Snilay@cs.wisc.edu 4710008Snilay@cs.wisc.edu# 4810008Snilay@cs.wisc.edu# Note: the L2 Cache latency is not currently used 4910008Snilay@cs.wisc.edu# 5010008Snilay@cs.wisc.educlass L2Cache(RubyCache): 5110008Snilay@cs.wisc.edu latency = 15 5210008Snilay@cs.wisc.edu 5310008Snilay@cs.wisc.edudef define_options(parser): 5410008Snilay@cs.wisc.edu parser.add_option("--num-clusters", type="int", default=1, 5510008Snilay@cs.wisc.edu help="number of clusters in a design in which there are shared\ 5610008Snilay@cs.wisc.edu caches private to clusters") 5710008Snilay@cs.wisc.edu return 5810008Snilay@cs.wisc.edu 5910116Snilay@cs.wisc.edudef create_system(options, system, dma_ports, ruby_system): 6010008Snilay@cs.wisc.edu 6110008Snilay@cs.wisc.edu if buildEnv['PROTOCOL'] != 'MESI_Three_Level': 6210008Snilay@cs.wisc.edu fatal("This script requires the MESI_Three_Level protocol to be built.") 6310008Snilay@cs.wisc.edu 6410008Snilay@cs.wisc.edu cpu_sequencers = [] 6510008Snilay@cs.wisc.edu 6610008Snilay@cs.wisc.edu # 6710008Snilay@cs.wisc.edu # The ruby network creation expects the list of nodes in the system to be 6810008Snilay@cs.wisc.edu # consistent with the NetDest list. Therefore the l1 controller nodes must be 6910008Snilay@cs.wisc.edu # listed before the directory nodes and directory nodes before dma nodes, etc. 7010008Snilay@cs.wisc.edu # 7110008Snilay@cs.wisc.edu l0_cntrl_nodes = [] 7210008Snilay@cs.wisc.edu l1_cntrl_nodes = [] 7310008Snilay@cs.wisc.edu l2_cntrl_nodes = [] 7410008Snilay@cs.wisc.edu dir_cntrl_nodes = [] 7510008Snilay@cs.wisc.edu dma_cntrl_nodes = [] 7610008Snilay@cs.wisc.edu 7710008Snilay@cs.wisc.edu assert (options.num_cpus % options.num_clusters == 0) 7810008Snilay@cs.wisc.edu num_cpus_per_cluster = options.num_cpus / options.num_clusters 7910008Snilay@cs.wisc.edu 8010008Snilay@cs.wisc.edu assert (options.num_l2caches % options.num_clusters == 0) 8110008Snilay@cs.wisc.edu num_l2caches_per_cluster = options.num_l2caches / options.num_clusters 8210008Snilay@cs.wisc.edu 8310008Snilay@cs.wisc.edu l2_bits = int(math.log(num_l2caches_per_cluster, 2)) 8410008Snilay@cs.wisc.edu block_size_bits = int(math.log(options.cacheline_size, 2)) 8510008Snilay@cs.wisc.edu l2_index_start = block_size_bits + l2_bits 8610008Snilay@cs.wisc.edu 8710008Snilay@cs.wisc.edu # 8810008Snilay@cs.wisc.edu # Must create the individual controllers before the network to ensure the 8910008Snilay@cs.wisc.edu # controller constructors are called before the network constructor 9010008Snilay@cs.wisc.edu # 9110008Snilay@cs.wisc.edu for i in xrange(options.num_clusters): 9210008Snilay@cs.wisc.edu for j in xrange(num_cpus_per_cluster): 9310008Snilay@cs.wisc.edu # 9410008Snilay@cs.wisc.edu # First create the Ruby objects associated with this cpu 9510008Snilay@cs.wisc.edu # 9610008Snilay@cs.wisc.edu l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, 9710008Snilay@cs.wisc.edu start_index_bit = block_size_bits, replacement_policy="LRU") 9810008Snilay@cs.wisc.edu 9910008Snilay@cs.wisc.edu l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 10010008Snilay@cs.wisc.edu start_index_bit = block_size_bits, replacement_policy="LRU") 10110008Snilay@cs.wisc.edu 10210008Snilay@cs.wisc.edu l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j, 10310008Snilay@cs.wisc.edu Icache = l0i_cache, Dcache = l0d_cache, 10410008Snilay@cs.wisc.edu send_evictions = (options.cpu_type == "detailed"), 10510008Snilay@cs.wisc.edu ruby_system = ruby_system) 10610008Snilay@cs.wisc.edu 10710008Snilay@cs.wisc.edu cpu_seq = RubySequencer(version = i, icache = l0i_cache, 10810008Snilay@cs.wisc.edu dcache = l0d_cache, ruby_system = ruby_system) 10910008Snilay@cs.wisc.edu 11010008Snilay@cs.wisc.edu l0_cntrl.sequencer = cpu_seq 11110008Snilay@cs.wisc.edu 11210008Snilay@cs.wisc.edu l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 11310008Snilay@cs.wisc.edu start_index_bit = block_size_bits, is_icache = False) 11410008Snilay@cs.wisc.edu 11510008Snilay@cs.wisc.edu l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, 11610008Snilay@cs.wisc.edu cache = l1_cache, l2_select_num_bits = l2_bits, 11710008Snilay@cs.wisc.edu cluster_id = i, ruby_system = ruby_system) 11810008Snilay@cs.wisc.edu 11910008Snilay@cs.wisc.edu exec("ruby_system.l0_cntrl%d = l0_cntrl" % ( 12010008Snilay@cs.wisc.edu i*num_cpus_per_cluster+j)) 12110008Snilay@cs.wisc.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % ( 12210008Snilay@cs.wisc.edu i*num_cpus_per_cluster+j)) 12310008Snilay@cs.wisc.edu 12410008Snilay@cs.wisc.edu # 12510008Snilay@cs.wisc.edu # Add controllers and sequencers to the appropriate lists 12610008Snilay@cs.wisc.edu # 12710008Snilay@cs.wisc.edu cpu_sequencers.append(cpu_seq) 12810008Snilay@cs.wisc.edu l0_cntrl_nodes.append(l0_cntrl) 12910008Snilay@cs.wisc.edu l1_cntrl_nodes.append(l1_cntrl) 13010008Snilay@cs.wisc.edu l0_cntrl.peer = l1_cntrl 13110008Snilay@cs.wisc.edu 13210008Snilay@cs.wisc.edu for j in xrange(num_l2caches_per_cluster): 13310008Snilay@cs.wisc.edu l2_cache = L2Cache(size = options.l2_size, 13410008Snilay@cs.wisc.edu assoc = options.l2_assoc, 13510008Snilay@cs.wisc.edu start_index_bit = l2_index_start) 13610008Snilay@cs.wisc.edu 13710008Snilay@cs.wisc.edu l2_cntrl = L2Cache_Controller( 13810008Snilay@cs.wisc.edu version = i * num_l2caches_per_cluster + j, 13910008Snilay@cs.wisc.edu L2cache = l2_cache, cluster_id = i, 14010008Snilay@cs.wisc.edu transitions_per_cycle=options.ports, 14110008Snilay@cs.wisc.edu ruby_system = ruby_system) 14210008Snilay@cs.wisc.edu 14310008Snilay@cs.wisc.edu exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 14410008Snilay@cs.wisc.edu i * num_l2caches_per_cluster + j)) 14510008Snilay@cs.wisc.edu l2_cntrl_nodes.append(l2_cntrl) 14610008Snilay@cs.wisc.edu 14710008Snilay@cs.wisc.edu phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 14810008Snilay@cs.wisc.edu assert(phys_mem_size % options.num_dirs == 0) 14910008Snilay@cs.wisc.edu mem_module_size = phys_mem_size / options.num_dirs 15010008Snilay@cs.wisc.edu 15110008Snilay@cs.wisc.edu # Run each of the ruby memory controllers at a ratio of the frequency of 15210008Snilay@cs.wisc.edu # the ruby system 15310008Snilay@cs.wisc.edu # clk_divider value is a fix to pass regression. 15410008Snilay@cs.wisc.edu ruby_system.memctrl_clk_domain = DerivedClockDomain( 15510008Snilay@cs.wisc.edu clk_domain=ruby_system.clk_domain, 15610008Snilay@cs.wisc.edu clk_divider=3) 15710008Snilay@cs.wisc.edu 15810008Snilay@cs.wisc.edu for i in xrange(options.num_dirs): 15910008Snilay@cs.wisc.edu # 16010008Snilay@cs.wisc.edu # Create the Ruby objects associated with the directory controller 16110008Snilay@cs.wisc.edu # 16210008Snilay@cs.wisc.edu 16310008Snilay@cs.wisc.edu mem_cntrl = RubyMemoryControl( 16410008Snilay@cs.wisc.edu clk_domain = ruby_system.memctrl_clk_domain, 16510008Snilay@cs.wisc.edu version = i, 16610008Snilay@cs.wisc.edu ruby_system = ruby_system) 16710008Snilay@cs.wisc.edu 16810008Snilay@cs.wisc.edu dir_size = MemorySize('0B') 16910008Snilay@cs.wisc.edu dir_size.value = mem_module_size 17010008Snilay@cs.wisc.edu 17110008Snilay@cs.wisc.edu dir_cntrl = Directory_Controller(version = i, 17210008Snilay@cs.wisc.edu directory = \ 17310008Snilay@cs.wisc.edu RubyDirectoryMemory(version = i, 17410008Snilay@cs.wisc.edu size = dir_size, 17510008Snilay@cs.wisc.edu use_map = 17610008Snilay@cs.wisc.edu options.use_map), 17710008Snilay@cs.wisc.edu memBuffer = mem_cntrl, 17810008Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 17910008Snilay@cs.wisc.edu ruby_system = ruby_system) 18010008Snilay@cs.wisc.edu 18110008Snilay@cs.wisc.edu exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 18210008Snilay@cs.wisc.edu dir_cntrl_nodes.append(dir_cntrl) 18310008Snilay@cs.wisc.edu 18410008Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 18510008Snilay@cs.wisc.edu # 18610008Snilay@cs.wisc.edu # Create the Ruby objects associated with the dma controller 18710008Snilay@cs.wisc.edu # 18810008Snilay@cs.wisc.edu dma_seq = DMASequencer(version = i, 18910008Snilay@cs.wisc.edu ruby_system = ruby_system) 19010008Snilay@cs.wisc.edu 19110008Snilay@cs.wisc.edu dma_cntrl = DMA_Controller(version = i, 19210008Snilay@cs.wisc.edu dma_sequencer = dma_seq, 19310008Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 19410008Snilay@cs.wisc.edu ruby_system = ruby_system) 19510008Snilay@cs.wisc.edu 19610008Snilay@cs.wisc.edu exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 19710008Snilay@cs.wisc.edu exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 19810008Snilay@cs.wisc.edu dma_cntrl_nodes.append(dma_cntrl) 19910008Snilay@cs.wisc.edu 20010008Snilay@cs.wisc.edu all_cntrls = l0_cntrl_nodes + \ 20110008Snilay@cs.wisc.edu l1_cntrl_nodes + \ 20210008Snilay@cs.wisc.edu l2_cntrl_nodes + \ 20310008Snilay@cs.wisc.edu dir_cntrl_nodes + \ 20410008Snilay@cs.wisc.edu dma_cntrl_nodes 20510008Snilay@cs.wisc.edu 20610008Snilay@cs.wisc.edu topology = create_topology(all_cntrls, options) 20710008Snilay@cs.wisc.edu return (cpu_sequencers, dir_cntrl_nodes, topology) 208