Garnet_standalone.py revision 12976:125099a94768
17404SAli.Saidi@ARM.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 27404SAli.Saidi@ARM.com# Copyright (c) 2016 Georgia Institute of Technology 37404SAli.Saidi@ARM.com# All rights reserved. 47404SAli.Saidi@ARM.com# 57404SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without 67404SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are 77404SAli.Saidi@ARM.com# met: redistributions of source code must retain the above copyright 87404SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer; 97404SAli.Saidi@ARM.com# redistributions in binary form must reproduce the above copyright 107404SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer in the 117404SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution; 127404SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its 137404SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from 147404SAli.Saidi@ARM.com# this software without specific prior written permission. 157404SAli.Saidi@ARM.com# 167404SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177404SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187404SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197404SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207404SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217404SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227404SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237404SAli.Saidi@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247404SAli.Saidi@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257404SAli.Saidi@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267404SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277404SAli.Saidi@ARM.com# 287404SAli.Saidi@ARM.com# Authors: Brad Beckmann 297404SAli.Saidi@ARM.com# Tushar Krishna 307404SAli.Saidi@ARM.com 317404SAli.Saidi@ARM.comimport m5 327404SAli.Saidi@ARM.comfrom m5.objects import * 337404SAli.Saidi@ARM.comfrom m5.defines import buildEnv 347404SAli.Saidi@ARM.comfrom m5.util import addToPath 357404SAli.Saidi@ARM.comfrom Ruby import create_topology, create_directories 367404SAli.Saidi@ARM.com 377404SAli.Saidi@ARM.com# 387404SAli.Saidi@ARM.com# Declare caches used by the protocol 397404SAli.Saidi@ARM.com# 407404SAli.Saidi@ARM.comclass L1Cache(RubyCache): pass 417404SAli.Saidi@ARM.com 427404SAli.Saidi@ARM.comdef define_options(parser): 437404SAli.Saidi@ARM.com return 447404SAli.Saidi@ARM.com 457404SAli.Saidi@ARM.comdef create_system(options, full_system, system, dma_ports, bootmem, 467404SAli.Saidi@ARM.com ruby_system): 477404SAli.Saidi@ARM.com if buildEnv['PROTOCOL'] != 'Garnet_standalone': 487404SAli.Saidi@ARM.com panic("This script requires Garnet_standalone protocol to be built.") 497404SAli.Saidi@ARM.com 507404SAli.Saidi@ARM.com cpu_sequencers = [] 517404SAli.Saidi@ARM.com 527404SAli.Saidi@ARM.com # 537404SAli.Saidi@ARM.com # The Garnet_standalone protocol does not support fs nor dma 547404SAli.Saidi@ARM.com # 557404SAli.Saidi@ARM.com assert(dma_ports == []) 567404SAli.Saidi@ARM.com 577404SAli.Saidi@ARM.com # 587404SAli.Saidi@ARM.com # The ruby network creation expects the list of nodes in the system to be 597404SAli.Saidi@ARM.com # consistent with the NetDest list. 607404SAli.Saidi@ARM.com # Therefore the l1 controller nodes must be listed before 617404SAli.Saidi@ARM.com # the directory nodes and directory nodes before dma nodes, etc. 627404SAli.Saidi@ARM.com l1_cntrl_nodes = [] 637404SAli.Saidi@ARM.com 647404SAli.Saidi@ARM.com # 657404SAli.Saidi@ARM.com # Must create the individual controllers before the network to ensure the 667404SAli.Saidi@ARM.com # controller constructors are called before the network constructor 677404SAli.Saidi@ARM.com # 687404SAli.Saidi@ARM.com 697404SAli.Saidi@ARM.com for i in xrange(options.num_cpus): 707404SAli.Saidi@ARM.com # 717404SAli.Saidi@ARM.com # First create the Ruby objects associated with this cpu 727404SAli.Saidi@ARM.com # Only one cache exists for this protocol, so by default use the L1D 737404SAli.Saidi@ARM.com # config parameters. 747404SAli.Saidi@ARM.com # 757404SAli.Saidi@ARM.com cache = L1Cache(size = options.l1d_size, 767404SAli.Saidi@ARM.com assoc = options.l1d_assoc) 777404SAli.Saidi@ARM.com 787404SAli.Saidi@ARM.com # 797404SAli.Saidi@ARM.com # Only one unified L1 cache exists. Can cache instructions and data. 807404SAli.Saidi@ARM.com # 817404SAli.Saidi@ARM.com l1_cntrl = L1Cache_Controller(version = i, 827404SAli.Saidi@ARM.com cacheMemory = cache, 837404SAli.Saidi@ARM.com ruby_system = ruby_system) 847404SAli.Saidi@ARM.com 857404SAli.Saidi@ARM.com cpu_seq = RubySequencer(icache = cache, 867404SAli.Saidi@ARM.com dcache = cache, 877404SAli.Saidi@ARM.com garnet_standalone = True, 887404SAli.Saidi@ARM.com ruby_system = ruby_system) 897404SAli.Saidi@ARM.com 907404SAli.Saidi@ARM.com l1_cntrl.sequencer = cpu_seq 917404SAli.Saidi@ARM.com exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 927404SAli.Saidi@ARM.com 937404SAli.Saidi@ARM.com # Add controllers and sequencers to the appropriate lists 947404SAli.Saidi@ARM.com cpu_sequencers.append(cpu_seq) 957404SAli.Saidi@ARM.com l1_cntrl_nodes.append(l1_cntrl) 967404SAli.Saidi@ARM.com 977404SAli.Saidi@ARM.com # Connect the L1 controllers and the network 987404SAli.Saidi@ARM.com l1_cntrl.mandatoryQueue = MessageBuffer() 997404SAli.Saidi@ARM.com l1_cntrl.requestFromCache = MessageBuffer() 1007404SAli.Saidi@ARM.com l1_cntrl.responseFromCache = MessageBuffer() 1017404SAli.Saidi@ARM.com l1_cntrl.forwardFromCache = MessageBuffer() 1027404SAli.Saidi@ARM.com 1037404SAli.Saidi@ARM.com mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( 1047404SAli.Saidi@ARM.com options, bootmem, ruby_system, system) 1057404SAli.Saidi@ARM.com dir_cntrl_nodes = mem_dir_cntrl_nodes[:] 1067404SAli.Saidi@ARM.com if rom_dir_cntrl_node is not None: 1077404SAli.Saidi@ARM.com dir_cntrl_nodes.append(rom_dir_cntrl_node) 1087404SAli.Saidi@ARM.com for dir_cntrl in dir_cntrl_nodes: 1097404SAli.Saidi@ARM.com # Connect the directory controllers and the network 1107404SAli.Saidi@ARM.com dir_cntrl.requestToDir = MessageBuffer() 1117404SAli.Saidi@ARM.com dir_cntrl.forwardToDir = MessageBuffer() 1127404SAli.Saidi@ARM.com dir_cntrl.responseToDir = MessageBuffer() 1137404SAli.Saidi@ARM.com 1147404SAli.Saidi@ARM.com 1157404SAli.Saidi@ARM.com all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes 1167404SAli.Saidi@ARM.com ruby_system.network.number_of_virtual_networks = 3 1177404SAli.Saidi@ARM.com topology = create_topology(all_cntrls, options) 1187404SAli.Saidi@ARM.com return (cpu_sequencers, mem_dir_cntrl_nodes, topology) 1197404SAli.Saidi@ARM.com