GPU_VIPER_Baseline.py revision 13731
112647Santhony.gutierrez@amd.com# Copyright (c) 2015 Advanced Micro Devices, Inc. 212647Santhony.gutierrez@amd.com# All rights reserved. 311308Santhony.gutierrez@amd.com# 412647Santhony.gutierrez@amd.com# For use for simulation and test purposes only 511308Santhony.gutierrez@amd.com# 612647Santhony.gutierrez@amd.com# Redistribution and use in source and binary forms, with or without 712647Santhony.gutierrez@amd.com# modification, are permitted provided that the following conditions are met: 811308Santhony.gutierrez@amd.com# 912647Santhony.gutierrez@amd.com# 1. Redistributions of source code must retain the above copyright notice, 1012647Santhony.gutierrez@amd.com# this list of conditions and the following disclaimer. 1111308Santhony.gutierrez@amd.com# 1212647Santhony.gutierrez@amd.com# 2. Redistributions in binary form must reproduce the above copyright notice, 1312647Santhony.gutierrez@amd.com# this list of conditions and the following disclaimer in the documentation 1412647Santhony.gutierrez@amd.com# and/or other materials provided with the distribution. 1511308Santhony.gutierrez@amd.com# 1612647Santhony.gutierrez@amd.com# 3. Neither the name of the copyright holder nor the names of its 1712647Santhony.gutierrez@amd.com# contributors may be used to endorse or promote products derived from this 1812647Santhony.gutierrez@amd.com# software without specific prior written permission. 1911308Santhony.gutierrez@amd.com# 2012647Santhony.gutierrez@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2112647Santhony.gutierrez@amd.com# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2212647Santhony.gutierrez@amd.com# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2312647Santhony.gutierrez@amd.com# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2412647Santhony.gutierrez@amd.com# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2512647Santhony.gutierrez@amd.com# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2612647Santhony.gutierrez@amd.com# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2712647Santhony.gutierrez@amd.com# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2812647Santhony.gutierrez@amd.com# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2912647Santhony.gutierrez@amd.com# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3012647Santhony.gutierrez@amd.com# POSSIBILITY OF SUCH DAMAGE. 3111308Santhony.gutierrez@amd.com# 3212647Santhony.gutierrez@amd.com# Authors: Sooraj Puthoor 3311308Santhony.gutierrez@amd.com 3411308Santhony.gutierrez@amd.comimport math 3511308Santhony.gutierrez@amd.comimport m5 3611308Santhony.gutierrez@amd.comfrom m5.objects import * 3711308Santhony.gutierrez@amd.comfrom m5.defines import buildEnv 3813400Sodanrc@yahoo.com.brfrom m5.util import addToPath 3911308Santhony.gutierrez@amd.comfrom Ruby import create_topology 4011308Santhony.gutierrez@amd.comfrom Ruby import send_evicts 4111308Santhony.gutierrez@amd.com 4213400Sodanrc@yahoo.com.braddToPath('../') 4313400Sodanrc@yahoo.com.br 4411670Sandreas.hansson@arm.comfrom topologies.Cluster import Cluster 4511670Sandreas.hansson@arm.comfrom topologies.Crossbar import Crossbar 4611308Santhony.gutierrez@amd.com 4711308Santhony.gutierrez@amd.comclass CntrlBase: 4811308Santhony.gutierrez@amd.com _seqs = 0 4911308Santhony.gutierrez@amd.com @classmethod 5011308Santhony.gutierrez@amd.com def seqCount(cls): 5111308Santhony.gutierrez@amd.com # Use SeqCount not class since we need global count 5211308Santhony.gutierrez@amd.com CntrlBase._seqs += 1 5311308Santhony.gutierrez@amd.com return CntrlBase._seqs - 1 5411308Santhony.gutierrez@amd.com 5511308Santhony.gutierrez@amd.com _cntrls = 0 5611308Santhony.gutierrez@amd.com @classmethod 5711308Santhony.gutierrez@amd.com def cntrlCount(cls): 5811308Santhony.gutierrez@amd.com # Use CntlCount not class since we need global count 5911308Santhony.gutierrez@amd.com CntrlBase._cntrls += 1 6011308Santhony.gutierrez@amd.com return CntrlBase._cntrls - 1 6111308Santhony.gutierrez@amd.com 6211308Santhony.gutierrez@amd.com _version = 0 6311308Santhony.gutierrez@amd.com @classmethod 6411308Santhony.gutierrez@amd.com def versionCount(cls): 6511308Santhony.gutierrez@amd.com cls._version += 1 # Use count for this particular type 6611308Santhony.gutierrez@amd.com return cls._version - 1 6711308Santhony.gutierrez@amd.com 6811308Santhony.gutierrez@amd.comclass L1Cache(RubyCache): 6911308Santhony.gutierrez@amd.com resourceStalls = False 7011308Santhony.gutierrez@amd.com dataArrayBanks = 2 7111308Santhony.gutierrez@amd.com tagArrayBanks = 2 7211308Santhony.gutierrez@amd.com dataAccessLatency = 1 7311308Santhony.gutierrez@amd.com tagAccessLatency = 1 7411308Santhony.gutierrez@amd.com def create(self, size, assoc, options): 7511308Santhony.gutierrez@amd.com self.size = MemorySize(size) 7611308Santhony.gutierrez@amd.com self.assoc = assoc 7711308Santhony.gutierrez@amd.com self.replacement_policy = PseudoLRUReplacementPolicy() 7811308Santhony.gutierrez@amd.com 7911308Santhony.gutierrez@amd.comclass L2Cache(RubyCache): 8011308Santhony.gutierrez@amd.com resourceStalls = False 8111308Santhony.gutierrez@amd.com assoc = 16 8211308Santhony.gutierrez@amd.com dataArrayBanks = 16 8311308Santhony.gutierrez@amd.com tagArrayBanks = 16 8411308Santhony.gutierrez@amd.com def create(self, size, assoc, options): 8511308Santhony.gutierrez@amd.com self.size = MemorySize(size) 8611308Santhony.gutierrez@amd.com self.assoc = assoc 8711308Santhony.gutierrez@amd.com self.replacement_policy = PseudoLRUReplacementPolicy() 8811308Santhony.gutierrez@amd.com 8911308Santhony.gutierrez@amd.comclass CPCntrl(CorePair_Controller, CntrlBase): 9011308Santhony.gutierrez@amd.com 9111308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 9211308Santhony.gutierrez@amd.com self.version = self.versionCount() 9311308Santhony.gutierrez@amd.com 9411308Santhony.gutierrez@amd.com self.L1Icache = L1Cache() 9511308Santhony.gutierrez@amd.com self.L1Icache.create(options.l1i_size, options.l1i_assoc, options) 9611308Santhony.gutierrez@amd.com self.L1D0cache = L1Cache() 9711308Santhony.gutierrez@amd.com self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options) 9811308Santhony.gutierrez@amd.com self.L1D1cache = L1Cache() 9911308Santhony.gutierrez@amd.com self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options) 10011308Santhony.gutierrez@amd.com self.L2cache = L2Cache() 10111308Santhony.gutierrez@amd.com self.L2cache.create(options.l2_size, options.l2_assoc, options) 10211308Santhony.gutierrez@amd.com 10311308Santhony.gutierrez@amd.com self.sequencer = RubySequencer() 10411308Santhony.gutierrez@amd.com self.sequencer.version = self.seqCount() 10511308Santhony.gutierrez@amd.com self.sequencer.icache = self.L1Icache 10611308Santhony.gutierrez@amd.com self.sequencer.dcache = self.L1D0cache 10711308Santhony.gutierrez@amd.com self.sequencer.ruby_system = ruby_system 10811308Santhony.gutierrez@amd.com self.sequencer.coreid = 0 10911308Santhony.gutierrez@amd.com self.sequencer.is_cpu_sequencer = True 11011308Santhony.gutierrez@amd.com 11111308Santhony.gutierrez@amd.com self.sequencer1 = RubySequencer() 11211308Santhony.gutierrez@amd.com self.sequencer1.version = self.seqCount() 11311308Santhony.gutierrez@amd.com self.sequencer1.icache = self.L1Icache 11411308Santhony.gutierrez@amd.com self.sequencer1.dcache = self.L1D1cache 11511308Santhony.gutierrez@amd.com self.sequencer1.ruby_system = ruby_system 11611308Santhony.gutierrez@amd.com self.sequencer1.coreid = 1 11711308Santhony.gutierrez@amd.com self.sequencer1.is_cpu_sequencer = True 11811308Santhony.gutierrez@amd.com 11911308Santhony.gutierrez@amd.com self.issue_latency = options.cpu_to_dir_latency 12011308Santhony.gutierrez@amd.com self.send_evictions = send_evicts(options) 12111308Santhony.gutierrez@amd.com 12211308Santhony.gutierrez@amd.com self.ruby_system = ruby_system 12311308Santhony.gutierrez@amd.com 12411308Santhony.gutierrez@amd.com if options.recycle_latency: 12511308Santhony.gutierrez@amd.com self.recycle_latency = options.recycle_latency 12611308Santhony.gutierrez@amd.com 12711308Santhony.gutierrez@amd.comclass TCPCache(RubyCache): 12811308Santhony.gutierrez@amd.com size = "16kB" 12911308Santhony.gutierrez@amd.com assoc = 16 13011308Santhony.gutierrez@amd.com dataArrayBanks = 16 13111308Santhony.gutierrez@amd.com tagArrayBanks = 16 13211308Santhony.gutierrez@amd.com dataAccessLatency = 4 13311308Santhony.gutierrez@amd.com tagAccessLatency = 1 13411308Santhony.gutierrez@amd.com def create(self, options): 13511308Santhony.gutierrez@amd.com self.size = MemorySize(options.tcp_size) 13611308Santhony.gutierrez@amd.com self.dataArrayBanks = 16 13711308Santhony.gutierrez@amd.com self.tagArrayBanks = 16 13811308Santhony.gutierrez@amd.com self.dataAccessLatency = 4 13911308Santhony.gutierrez@amd.com self.tagAccessLatency = 1 14011308Santhony.gutierrez@amd.com self.resourceStalls = options.no_tcc_resource_stalls 14111308Santhony.gutierrez@amd.com self.replacement_policy = PseudoLRUReplacementPolicy() 14211308Santhony.gutierrez@amd.com 14311308Santhony.gutierrez@amd.comclass TCPCntrl(TCP_Controller, CntrlBase): 14411308Santhony.gutierrez@amd.com 14511308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 14611308Santhony.gutierrez@amd.com self.version = self.versionCount() 14711308Santhony.gutierrez@amd.com self.L1cache = TCPCache() 14811308Santhony.gutierrez@amd.com self.L1cache.create(options) 14911308Santhony.gutierrez@amd.com self.issue_latency = 1 15011308Santhony.gutierrez@amd.com 15111308Santhony.gutierrez@amd.com self.coalescer = VIPERCoalescer() 15211308Santhony.gutierrez@amd.com self.coalescer.version = self.seqCount() 15311308Santhony.gutierrez@amd.com self.coalescer.icache = self.L1cache 15411308Santhony.gutierrez@amd.com self.coalescer.dcache = self.L1cache 15511308Santhony.gutierrez@amd.com self.coalescer.ruby_system = ruby_system 15611308Santhony.gutierrez@amd.com self.coalescer.support_inst_reqs = False 15711308Santhony.gutierrez@amd.com self.coalescer.is_cpu_sequencer = False 15811308Santhony.gutierrez@amd.com 15911308Santhony.gutierrez@amd.com self.sequencer = RubySequencer() 16011308Santhony.gutierrez@amd.com self.sequencer.version = self.seqCount() 16111308Santhony.gutierrez@amd.com self.sequencer.icache = self.L1cache 16211308Santhony.gutierrez@amd.com self.sequencer.dcache = self.L1cache 16311308Santhony.gutierrez@amd.com self.sequencer.ruby_system = ruby_system 16411308Santhony.gutierrez@amd.com self.sequencer.is_cpu_sequencer = True 16511308Santhony.gutierrez@amd.com 16611308Santhony.gutierrez@amd.com self.use_seq_not_coal = False 16711308Santhony.gutierrez@amd.com 16811308Santhony.gutierrez@amd.com self.ruby_system = ruby_system 16911308Santhony.gutierrez@amd.com if options.recycle_latency: 17011308Santhony.gutierrez@amd.com self.recycle_latency = options.recycle_latency 17111308Santhony.gutierrez@amd.com 17211308Santhony.gutierrez@amd.comclass SQCCache(RubyCache): 17311308Santhony.gutierrez@amd.com dataArrayBanks = 8 17411308Santhony.gutierrez@amd.com tagArrayBanks = 8 17511308Santhony.gutierrez@amd.com dataAccessLatency = 1 17611308Santhony.gutierrez@amd.com tagAccessLatency = 1 17711308Santhony.gutierrez@amd.com 17811308Santhony.gutierrez@amd.com def create(self, options): 17911308Santhony.gutierrez@amd.com self.size = MemorySize(options.sqc_size) 18011308Santhony.gutierrez@amd.com self.assoc = options.sqc_assoc 18111308Santhony.gutierrez@amd.com self.replacement_policy = PseudoLRUReplacementPolicy() 18211308Santhony.gutierrez@amd.com 18311308Santhony.gutierrez@amd.comclass SQCCntrl(SQC_Controller, CntrlBase): 18411308Santhony.gutierrez@amd.com 18511308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 18611308Santhony.gutierrez@amd.com self.version = self.versionCount() 18711308Santhony.gutierrez@amd.com self.L1cache = SQCCache() 18811308Santhony.gutierrez@amd.com self.L1cache.create(options) 18911308Santhony.gutierrez@amd.com self.L1cache.resourceStalls = False 19011308Santhony.gutierrez@amd.com self.sequencer = RubySequencer() 19111308Santhony.gutierrez@amd.com self.sequencer.version = self.seqCount() 19211308Santhony.gutierrez@amd.com self.sequencer.icache = self.L1cache 19311308Santhony.gutierrez@amd.com self.sequencer.dcache = self.L1cache 19411308Santhony.gutierrez@amd.com self.sequencer.ruby_system = ruby_system 19511308Santhony.gutierrez@amd.com self.sequencer.support_data_reqs = False 19611308Santhony.gutierrez@amd.com self.sequencer.is_cpu_sequencer = False 19711308Santhony.gutierrez@amd.com self.ruby_system = ruby_system 19811308Santhony.gutierrez@amd.com if options.recycle_latency: 19911308Santhony.gutierrez@amd.com self.recycle_latency = options.recycle_latency 20011308Santhony.gutierrez@amd.com 20111308Santhony.gutierrez@amd.comclass TCC(RubyCache): 20211308Santhony.gutierrez@amd.com size = MemorySize("256kB") 20311308Santhony.gutierrez@amd.com assoc = 16 20411308Santhony.gutierrez@amd.com dataAccessLatency = 8 20511308Santhony.gutierrez@amd.com tagAccessLatency = 2 20611308Santhony.gutierrez@amd.com resourceStalls = True 20711308Santhony.gutierrez@amd.com def create(self, options): 20811308Santhony.gutierrez@amd.com self.assoc = options.tcc_assoc 20911308Santhony.gutierrez@amd.com if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 21011308Santhony.gutierrez@amd.com s = options.num_compute_units 21111308Santhony.gutierrez@amd.com tcc_size = s * 128 21211308Santhony.gutierrez@amd.com tcc_size = str(tcc_size)+'kB' 21311308Santhony.gutierrez@amd.com self.size = MemorySize(tcc_size) 21411308Santhony.gutierrez@amd.com self.dataArrayBanks = 64 21511308Santhony.gutierrez@amd.com self.tagArrayBanks = 64 21611308Santhony.gutierrez@amd.com else: 21711308Santhony.gutierrez@amd.com self.size = MemorySize(options.tcc_size) 21811308Santhony.gutierrez@amd.com self.dataArrayBanks = 256 / options.num_tccs #number of data banks 21911308Santhony.gutierrez@amd.com self.tagArrayBanks = 256 / options.num_tccs #number of tag banks 22011308Santhony.gutierrez@amd.com self.size.value = self.size.value / options.num_tccs 22111308Santhony.gutierrez@amd.com if ((self.size.value / long(self.assoc)) < 128): 22211308Santhony.gutierrez@amd.com self.size.value = long(128 * self.assoc) 22311308Santhony.gutierrez@amd.com self.start_index_bit = math.log(options.cacheline_size, 2) + \ 22411308Santhony.gutierrez@amd.com math.log(options.num_tccs, 2) 22511308Santhony.gutierrez@amd.com self.replacement_policy = PseudoLRUReplacementPolicy() 22611308Santhony.gutierrez@amd.com 22711308Santhony.gutierrez@amd.comclass TCCCntrl(TCC_Controller, CntrlBase): 22811308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 22911308Santhony.gutierrez@amd.com self.version = self.versionCount() 23011308Santhony.gutierrez@amd.com self.L2cache = TCC() 23111308Santhony.gutierrez@amd.com self.L2cache.create(options) 23211308Santhony.gutierrez@amd.com self.ruby_system = ruby_system 23311308Santhony.gutierrez@amd.com self.L2cache.resourceStalls = options.no_tcc_resource_stalls 23411308Santhony.gutierrez@amd.com 23511308Santhony.gutierrez@amd.com if options.recycle_latency: 23611308Santhony.gutierrez@amd.com self.recycle_latency = options.recycle_latency 23711308Santhony.gutierrez@amd.com 23811308Santhony.gutierrez@amd.comclass L3Cache(RubyCache): 23911308Santhony.gutierrez@amd.com dataArrayBanks = 16 24011308Santhony.gutierrez@amd.com tagArrayBanks = 16 24111308Santhony.gutierrez@amd.com 24211308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 24311308Santhony.gutierrez@amd.com self.size = MemorySize(options.l3_size) 24411308Santhony.gutierrez@amd.com self.size.value /= options.num_dirs 24511308Santhony.gutierrez@amd.com self.assoc = options.l3_assoc 24611308Santhony.gutierrez@amd.com self.dataArrayBanks /= options.num_dirs 24711308Santhony.gutierrez@amd.com self.tagArrayBanks /= options.num_dirs 24811308Santhony.gutierrez@amd.com self.dataArrayBanks /= options.num_dirs 24911308Santhony.gutierrez@amd.com self.tagArrayBanks /= options.num_dirs 25011308Santhony.gutierrez@amd.com self.dataAccessLatency = options.l3_data_latency 25111308Santhony.gutierrez@amd.com self.tagAccessLatency = options.l3_tag_latency 25211308Santhony.gutierrez@amd.com self.resourceStalls = False 25311308Santhony.gutierrez@amd.com self.replacement_policy = PseudoLRUReplacementPolicy() 25411308Santhony.gutierrez@amd.com 25511308Santhony.gutierrez@amd.comclass ProbeFilter(RubyCache): 25611308Santhony.gutierrez@amd.com size = "4MB" 25711308Santhony.gutierrez@amd.com assoc = 16 25811308Santhony.gutierrez@amd.com dataArrayBanks = 256 25911308Santhony.gutierrez@amd.com tagArrayBanks = 256 26011308Santhony.gutierrez@amd.com 26111308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 26211308Santhony.gutierrez@amd.com self.block_size = "%dB" % (64 * options.blocks_per_region) 26311308Santhony.gutierrez@amd.com self.size = options.region_dir_entries * \ 26411308Santhony.gutierrez@amd.com self.block_size * options.num_compute_units 26511308Santhony.gutierrez@amd.com self.assoc = 8 26611308Santhony.gutierrez@amd.com self.tagArrayBanks = 8 26711308Santhony.gutierrez@amd.com self.tagAccessLatency = options.dir_tag_latency 26811308Santhony.gutierrez@amd.com self.dataAccessLatency = 1 26911308Santhony.gutierrez@amd.com self.resourceStalls = options.no_resource_stalls 27011308Santhony.gutierrez@amd.com self.start_index_bit = 6 + int(math.log(options.blocks_per_region, 2)) 27111308Santhony.gutierrez@amd.com self.replacement_policy = PseudoLRUReplacementPolicy() 27211308Santhony.gutierrez@amd.com 27311308Santhony.gutierrez@amd.comclass L3Cntrl(L3Cache_Controller, CntrlBase): 27411308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 27511308Santhony.gutierrez@amd.com self.version = self.versionCount() 27611308Santhony.gutierrez@amd.com self.L3cache = L3Cache() 27711308Santhony.gutierrez@amd.com self.L3cache.create(options, ruby_system, system) 27811308Santhony.gutierrez@amd.com self.l3_response_latency = \ 27911308Santhony.gutierrez@amd.com max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency) 28011308Santhony.gutierrez@amd.com self.ruby_system = ruby_system 28111308Santhony.gutierrez@amd.com if options.recycle_latency: 28211308Santhony.gutierrez@amd.com self.recycle_latency = options.recycle_latency 28311308Santhony.gutierrez@amd.com 28411308Santhony.gutierrez@amd.com def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 28511308Santhony.gutierrez@amd.com req_to_l3, probe_to_l3, resp_to_l3): 28611308Santhony.gutierrez@amd.com self.reqToDir = req_to_dir 28711308Santhony.gutierrez@amd.com self.respToDir = resp_to_dir 28811308Santhony.gutierrez@amd.com self.l3UnblockToDir = l3_unblock_to_dir 28911308Santhony.gutierrez@amd.com self.reqToL3 = req_to_l3 29011308Santhony.gutierrez@amd.com self.probeToL3 = probe_to_l3 29111308Santhony.gutierrez@amd.com self.respToL3 = resp_to_l3 29211308Santhony.gutierrez@amd.com 29311308Santhony.gutierrez@amd.comclass DirMem(RubyDirectoryMemory, CntrlBase): 29411308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 29511308Santhony.gutierrez@amd.com self.version = self.versionCount() 29611308Santhony.gutierrez@amd.com 29711308Santhony.gutierrez@amd.com phys_mem_size = AddrRange(options.mem_size).size() 29811308Santhony.gutierrez@amd.com mem_module_size = phys_mem_size / options.num_dirs 29911308Santhony.gutierrez@amd.com dir_size = MemorySize('0B') 30011308Santhony.gutierrez@amd.com dir_size.value = mem_module_size 30111308Santhony.gutierrez@amd.com self.size = dir_size 30211308Santhony.gutierrez@amd.com 30311308Santhony.gutierrez@amd.comclass DirCntrl(Directory_Controller, CntrlBase): 30411308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 30511308Santhony.gutierrez@amd.com self.version = self.versionCount() 30611308Santhony.gutierrez@amd.com self.response_latency = 30 30711308Santhony.gutierrez@amd.com self.directory = DirMem() 30811308Santhony.gutierrez@amd.com self.directory.create(options, ruby_system, system) 30911308Santhony.gutierrez@amd.com self.L3CacheMemory = L3Cache() 31011308Santhony.gutierrez@amd.com self.L3CacheMemory.create(options, ruby_system, system) 31111308Santhony.gutierrez@amd.com self.ProbeFilterMemory = ProbeFilter() 31211308Santhony.gutierrez@amd.com self.ProbeFilterMemory.create(options, ruby_system, system) 31311308Santhony.gutierrez@amd.com self.l3_hit_latency = \ 31411308Santhony.gutierrez@amd.com max(self.L3CacheMemory.dataAccessLatency, 31511308Santhony.gutierrez@amd.com self.L3CacheMemory.tagAccessLatency) 31611308Santhony.gutierrez@amd.com 31711308Santhony.gutierrez@amd.com self.ruby_system = ruby_system 31811308Santhony.gutierrez@amd.com if options.recycle_latency: 31911308Santhony.gutierrez@amd.com self.recycle_latency = options.recycle_latency 32011308Santhony.gutierrez@amd.com 32111308Santhony.gutierrez@amd.com def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 32211308Santhony.gutierrez@amd.com req_to_l3, probe_to_l3, resp_to_l3): 32311308Santhony.gutierrez@amd.com self.reqToDir = req_to_dir 32411308Santhony.gutierrez@amd.com self.respToDir = resp_to_dir 32511308Santhony.gutierrez@amd.com self.l3UnblockToDir = l3_unblock_to_dir 32611308Santhony.gutierrez@amd.com self.reqToL3 = req_to_l3 32711308Santhony.gutierrez@amd.com self.probeToL3 = probe_to_l3 32811308Santhony.gutierrez@amd.com self.respToL3 = resp_to_l3 32911308Santhony.gutierrez@amd.com 33011308Santhony.gutierrez@amd.comdef define_options(parser): 33111308Santhony.gutierrez@amd.com parser.add_option("--num-subcaches", type = "int", default = 4) 33211308Santhony.gutierrez@amd.com parser.add_option("--l3-data-latency", type = "int", default = 20) 33311308Santhony.gutierrez@amd.com parser.add_option("--l3-tag-latency", type = "int", default = 15) 33411308Santhony.gutierrez@amd.com parser.add_option("--cpu-to-dir-latency", type = "int", default = 120) 33511308Santhony.gutierrez@amd.com parser.add_option("--gpu-to-dir-latency", type = "int", default = 120) 33611308Santhony.gutierrez@amd.com parser.add_option("--no-resource-stalls", action = "store_false", 33711308Santhony.gutierrez@amd.com default = True) 33811308Santhony.gutierrez@amd.com parser.add_option("--no-tcc-resource-stalls", action = "store_false", 33911308Santhony.gutierrez@amd.com default = True) 34011308Santhony.gutierrez@amd.com parser.add_option("--num-tbes", type = "int", default = 2560) 34111308Santhony.gutierrez@amd.com parser.add_option("--l2-latency", type = "int", default = 50) # load to use 34211308Santhony.gutierrez@amd.com parser.add_option("--num-tccs", type = "int", default = 1, 34311308Santhony.gutierrez@amd.com help = "number of TCC banks in the GPU") 34411308Santhony.gutierrez@amd.com parser.add_option("--sqc-size", type = 'string', default = '32kB', 34511308Santhony.gutierrez@amd.com help = "SQC cache size") 34611308Santhony.gutierrez@amd.com parser.add_option("--sqc-assoc", type = 'int', default = 8, 34711308Santhony.gutierrez@amd.com help = "SQC cache assoc") 34811308Santhony.gutierrez@amd.com parser.add_option("--region-dir-entries", type = "int", default = 8192) 34911308Santhony.gutierrez@amd.com parser.add_option("--dir-tag-latency", type = "int", default = 8) 35011308Santhony.gutierrez@amd.com parser.add_option("--dir-tag-banks", type = "int", default = 4) 35111308Santhony.gutierrez@amd.com parser.add_option("--blocks-per-region", type = "int", default = 1) 35211308Santhony.gutierrez@amd.com parser.add_option("--use-L3-on-WT", action = "store_true", default = False) 35311308Santhony.gutierrez@amd.com parser.add_option("--nonInclusiveDir", action = "store_true", 35411308Santhony.gutierrez@amd.com default = False) 35511308Santhony.gutierrez@amd.com parser.add_option("--WB_L1", action = "store_true", 35611308Santhony.gutierrez@amd.com default = False, help = "writeback L2") 35711308Santhony.gutierrez@amd.com parser.add_option("--WB_L2", action = "store_true", 35811308Santhony.gutierrez@amd.com default = False, help = "writeback L2") 35911308Santhony.gutierrez@amd.com parser.add_option("--TCP_latency", type = "int", 36011308Santhony.gutierrez@amd.com default = 4, help = "TCP latency") 36111308Santhony.gutierrez@amd.com parser.add_option("--TCC_latency", type = "int", 36211308Santhony.gutierrez@amd.com default = 16, help = "TCC latency") 36311308Santhony.gutierrez@amd.com parser.add_option("--tcc-size", type = 'string', default = '2MB', 36411308Santhony.gutierrez@amd.com help = "agregate tcc size") 36511308Santhony.gutierrez@amd.com parser.add_option("--tcc-assoc", type = 'int', default = 16, 36611308Santhony.gutierrez@amd.com help = "tcc assoc") 36711308Santhony.gutierrez@amd.com parser.add_option("--tcp-size", type = 'string', default = '16kB', 36811308Santhony.gutierrez@amd.com help = "tcp size") 36911308Santhony.gutierrez@amd.com parser.add_option("--sampler-sets", type = "int", default = 1024) 37011308Santhony.gutierrez@amd.com parser.add_option("--sampler-assoc", type = "int", default = 16) 37111308Santhony.gutierrez@amd.com parser.add_option("--sampler-counter", type = "int", default = 512) 37211308Santhony.gutierrez@amd.com parser.add_option("--noL1", action = "store_true", default = False, 37311308Santhony.gutierrez@amd.com help = "bypassL1") 37411308Santhony.gutierrez@amd.com parser.add_option("--noL2", action = "store_true", default = False, 37511308Santhony.gutierrez@amd.com help = "bypassL2") 37611308Santhony.gutierrez@amd.com 37712598Snikos.nikoleris@arm.comdef create_system(options, full_system, system, dma_devices, bootmem, 37812598Snikos.nikoleris@arm.com ruby_system): 37911308Santhony.gutierrez@amd.com if buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline': 38011308Santhony.gutierrez@amd.com panic("This script requires the" \ 38111308Santhony.gutierrez@amd.com "GPU_VIPER_Baseline protocol to be built.") 38211308Santhony.gutierrez@amd.com 38311308Santhony.gutierrez@amd.com cpu_sequencers = [] 38411308Santhony.gutierrez@amd.com 38511308Santhony.gutierrez@amd.com # 38611308Santhony.gutierrez@amd.com # The ruby network creation expects the list of nodes in the system to be 38711308Santhony.gutierrez@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes 38811308Santhony.gutierrez@amd.com # must be listed before the directory nodes and directory nodes before 38911308Santhony.gutierrez@amd.com # dma nodes, etc. 39011308Santhony.gutierrez@amd.com # 39111308Santhony.gutierrez@amd.com cp_cntrl_nodes = [] 39211308Santhony.gutierrez@amd.com tcp_cntrl_nodes = [] 39311308Santhony.gutierrez@amd.com sqc_cntrl_nodes = [] 39411308Santhony.gutierrez@amd.com tcc_cntrl_nodes = [] 39511308Santhony.gutierrez@amd.com dir_cntrl_nodes = [] 39611308Santhony.gutierrez@amd.com l3_cntrl_nodes = [] 39711308Santhony.gutierrez@amd.com 39811308Santhony.gutierrez@amd.com # 39911308Santhony.gutierrez@amd.com # Must create the individual controllers before the network to ensure the 40011308Santhony.gutierrez@amd.com # controller constructors are called before the network constructor 40111308Santhony.gutierrez@amd.com # 40211308Santhony.gutierrez@amd.com 40311308Santhony.gutierrez@amd.com # For an odd number of CPUs, still create the right number of controllers 40411308Santhony.gutierrez@amd.com TCC_bits = int(math.log(options.num_tccs, 2)) 40511308Santhony.gutierrez@amd.com 40611308Santhony.gutierrez@amd.com # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 40711308Santhony.gutierrez@amd.com # Clusters 40811308Santhony.gutierrez@amd.com crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock 40911308Santhony.gutierrez@amd.com mainCluster = Cluster(intBW = crossbar_bw) 41013731Sandreas.sandberg@arm.com for i in range(options.num_dirs): 41111308Santhony.gutierrez@amd.com 41211308Santhony.gutierrez@amd.com dir_cntrl = DirCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits) 41311308Santhony.gutierrez@amd.com dir_cntrl.create(options, ruby_system, system) 41411308Santhony.gutierrez@amd.com dir_cntrl.number_of_TBEs = options.num_tbes 41511308Santhony.gutierrez@amd.com dir_cntrl.useL3OnWT = options.use_L3_on_WT 41611308Santhony.gutierrez@amd.com dir_cntrl.inclusiveDir = not options.nonInclusiveDir 41711308Santhony.gutierrez@amd.com 41811308Santhony.gutierrez@amd.com # Connect the Directory controller to the ruby network 41911308Santhony.gutierrez@amd.com dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 42011308Santhony.gutierrez@amd.com dir_cntrl.requestFromCores.slave = ruby_system.network.master 42111308Santhony.gutierrez@amd.com 42211308Santhony.gutierrez@amd.com dir_cntrl.responseFromCores = MessageBuffer() 42311308Santhony.gutierrez@amd.com dir_cntrl.responseFromCores.slave = ruby_system.network.master 42411308Santhony.gutierrez@amd.com 42511308Santhony.gutierrez@amd.com dir_cntrl.unblockFromCores = MessageBuffer() 42611308Santhony.gutierrez@amd.com dir_cntrl.unblockFromCores.slave = ruby_system.network.master 42711308Santhony.gutierrez@amd.com 42811308Santhony.gutierrez@amd.com dir_cntrl.probeToCore = MessageBuffer() 42911308Santhony.gutierrez@amd.com dir_cntrl.probeToCore.master = ruby_system.network.slave 43011308Santhony.gutierrez@amd.com 43111308Santhony.gutierrez@amd.com dir_cntrl.responseToCore = MessageBuffer() 43211308Santhony.gutierrez@amd.com dir_cntrl.responseToCore.master = ruby_system.network.slave 43311308Santhony.gutierrez@amd.com 43411308Santhony.gutierrez@amd.com dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 43511308Santhony.gutierrez@amd.com dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 43611308Santhony.gutierrez@amd.com dir_cntrl.responseFromMemory = MessageBuffer() 43711308Santhony.gutierrez@amd.com 43811308Santhony.gutierrez@amd.com exec("system.dir_cntrl%d = dir_cntrl" % i) 43911308Santhony.gutierrez@amd.com dir_cntrl_nodes.append(dir_cntrl) 44011308Santhony.gutierrez@amd.com mainCluster.add(dir_cntrl) 44111308Santhony.gutierrez@amd.com 44211308Santhony.gutierrez@amd.com cpuCluster = Cluster(extBW = crossbar_bw, intBW=crossbar_bw) 44313731Sandreas.sandberg@arm.com for i in range((options.num_cpus + 1) // 2): 44411308Santhony.gutierrez@amd.com 44511308Santhony.gutierrez@amd.com cp_cntrl = CPCntrl() 44611308Santhony.gutierrez@amd.com cp_cntrl.create(options, ruby_system, system) 44711308Santhony.gutierrez@amd.com 44811308Santhony.gutierrez@amd.com exec("system.cp_cntrl%d = cp_cntrl" % i) 44911308Santhony.gutierrez@amd.com # 45011308Santhony.gutierrez@amd.com # Add controllers and sequencers to the appropriate lists 45111308Santhony.gutierrez@amd.com # 45211308Santhony.gutierrez@amd.com cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 45311308Santhony.gutierrez@amd.com 45411308Santhony.gutierrez@amd.com # Connect the CP controllers and the network 45511308Santhony.gutierrez@amd.com cp_cntrl.requestFromCore = MessageBuffer() 45611308Santhony.gutierrez@amd.com cp_cntrl.requestFromCore.master = ruby_system.network.slave 45711308Santhony.gutierrez@amd.com 45811308Santhony.gutierrez@amd.com cp_cntrl.responseFromCore = MessageBuffer() 45911308Santhony.gutierrez@amd.com cp_cntrl.responseFromCore.master = ruby_system.network.slave 46011308Santhony.gutierrez@amd.com 46111308Santhony.gutierrez@amd.com cp_cntrl.unblockFromCore = MessageBuffer() 46211308Santhony.gutierrez@amd.com cp_cntrl.unblockFromCore.master = ruby_system.network.slave 46311308Santhony.gutierrez@amd.com 46411308Santhony.gutierrez@amd.com cp_cntrl.probeToCore = MessageBuffer() 46511308Santhony.gutierrez@amd.com cp_cntrl.probeToCore.slave = ruby_system.network.master 46611308Santhony.gutierrez@amd.com 46711308Santhony.gutierrez@amd.com cp_cntrl.responseToCore = MessageBuffer() 46811308Santhony.gutierrez@amd.com cp_cntrl.responseToCore.slave = ruby_system.network.master 46911308Santhony.gutierrez@amd.com 47011308Santhony.gutierrez@amd.com cp_cntrl.mandatoryQueue = MessageBuffer() 47111308Santhony.gutierrez@amd.com cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 47211308Santhony.gutierrez@amd.com 47311308Santhony.gutierrez@amd.com cpuCluster.add(cp_cntrl) 47411308Santhony.gutierrez@amd.com 47511308Santhony.gutierrez@amd.com gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw) 47613731Sandreas.sandberg@arm.com for i in range(options.num_compute_units): 47711308Santhony.gutierrez@amd.com 47811308Santhony.gutierrez@amd.com tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 47911308Santhony.gutierrez@amd.com issue_latency = 1, 48011308Santhony.gutierrez@amd.com number_of_TBEs = 2560) 48111308Santhony.gutierrez@amd.com # TBEs set to max outstanding requests 48211308Santhony.gutierrez@amd.com tcp_cntrl.create(options, ruby_system, system) 48311308Santhony.gutierrez@amd.com tcp_cntrl.WB = options.WB_L1 48411308Santhony.gutierrez@amd.com tcp_cntrl.disableL1 = options.noL1 48511308Santhony.gutierrez@amd.com 48611308Santhony.gutierrez@amd.com exec("system.tcp_cntrl%d = tcp_cntrl" % i) 48711308Santhony.gutierrez@amd.com # 48811308Santhony.gutierrez@amd.com # Add controllers and sequencers to the appropriate lists 48911308Santhony.gutierrez@amd.com # 49011308Santhony.gutierrez@amd.com cpu_sequencers.append(tcp_cntrl.coalescer) 49111308Santhony.gutierrez@amd.com tcp_cntrl_nodes.append(tcp_cntrl) 49211308Santhony.gutierrez@amd.com 49311308Santhony.gutierrez@amd.com # Connect the CP (TCP) controllers to the ruby network 49411308Santhony.gutierrez@amd.com tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 49511308Santhony.gutierrez@amd.com tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 49611308Santhony.gutierrez@amd.com 49711308Santhony.gutierrez@amd.com tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 49811308Santhony.gutierrez@amd.com tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 49911308Santhony.gutierrez@amd.com 50011308Santhony.gutierrez@amd.com tcp_cntrl.unblockFromCore = MessageBuffer() 50111308Santhony.gutierrez@amd.com tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 50211308Santhony.gutierrez@amd.com 50311308Santhony.gutierrez@amd.com tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 50411308Santhony.gutierrez@amd.com tcp_cntrl.probeToTCP.slave = ruby_system.network.master 50511308Santhony.gutierrez@amd.com 50611308Santhony.gutierrez@amd.com tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 50711308Santhony.gutierrez@amd.com tcp_cntrl.responseToTCP.slave = ruby_system.network.master 50811308Santhony.gutierrez@amd.com 50911308Santhony.gutierrez@amd.com tcp_cntrl.mandatoryQueue = MessageBuffer() 51011308Santhony.gutierrez@amd.com 51111308Santhony.gutierrez@amd.com gpuCluster.add(tcp_cntrl) 51211308Santhony.gutierrez@amd.com 51313731Sandreas.sandberg@arm.com for i in range(options.num_sqc): 51411308Santhony.gutierrez@amd.com 51511308Santhony.gutierrez@amd.com sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 51611308Santhony.gutierrez@amd.com sqc_cntrl.create(options, ruby_system, system) 51711308Santhony.gutierrez@amd.com 51811308Santhony.gutierrez@amd.com exec("system.sqc_cntrl%d = sqc_cntrl" % i) 51911308Santhony.gutierrez@amd.com # 52011308Santhony.gutierrez@amd.com # Add controllers and sequencers to the appropriate lists 52111308Santhony.gutierrez@amd.com # 52211308Santhony.gutierrez@amd.com cpu_sequencers.append(sqc_cntrl.sequencer) 52311308Santhony.gutierrez@amd.com 52411308Santhony.gutierrez@amd.com # Connect the SQC controller to the ruby network 52511308Santhony.gutierrez@amd.com sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True) 52611308Santhony.gutierrez@amd.com sqc_cntrl.requestFromSQC.master = ruby_system.network.slave 52711308Santhony.gutierrez@amd.com 52811308Santhony.gutierrez@amd.com sqc_cntrl.probeToSQC = MessageBuffer(ordered = True) 52911308Santhony.gutierrez@amd.com sqc_cntrl.probeToSQC.slave = ruby_system.network.master 53011308Santhony.gutierrez@amd.com 53111308Santhony.gutierrez@amd.com sqc_cntrl.responseToSQC = MessageBuffer(ordered = True) 53211308Santhony.gutierrez@amd.com sqc_cntrl.responseToSQC.slave = ruby_system.network.master 53311308Santhony.gutierrez@amd.com 53411308Santhony.gutierrez@amd.com sqc_cntrl.mandatoryQueue = MessageBuffer() 53511308Santhony.gutierrez@amd.com 53611308Santhony.gutierrez@amd.com # SQC also in GPU cluster 53711308Santhony.gutierrez@amd.com gpuCluster.add(sqc_cntrl) 53811308Santhony.gutierrez@amd.com 53911308Santhony.gutierrez@amd.com # Because of wire buffers, num_tccs must equal num_tccdirs 54011308Santhony.gutierrez@amd.com numa_bit = 6 54111308Santhony.gutierrez@amd.com 54213731Sandreas.sandberg@arm.com for i in range(options.num_tccs): 54311308Santhony.gutierrez@amd.com 54411308Santhony.gutierrez@amd.com tcc_cntrl = TCCCntrl() 54511308Santhony.gutierrez@amd.com tcc_cntrl.create(options, ruby_system, system) 54611308Santhony.gutierrez@amd.com tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency 54711308Santhony.gutierrez@amd.com tcc_cntrl.l2_response_latency = options.TCC_latency 54811308Santhony.gutierrez@amd.com tcc_cntrl_nodes.append(tcc_cntrl) 54911308Santhony.gutierrez@amd.com tcc_cntrl.WB = options.WB_L2 55011308Santhony.gutierrez@amd.com tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units 55111308Santhony.gutierrez@amd.com 55211308Santhony.gutierrez@amd.com # Connect the TCC controllers to the ruby network 55311308Santhony.gutierrez@amd.com tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True) 55411308Santhony.gutierrez@amd.com tcc_cntrl.requestFromTCP.slave = ruby_system.network.master 55511308Santhony.gutierrez@amd.com 55611308Santhony.gutierrez@amd.com tcc_cntrl.responseToCore = MessageBuffer(ordered = True) 55711308Santhony.gutierrez@amd.com tcc_cntrl.responseToCore.master = ruby_system.network.slave 55811308Santhony.gutierrez@amd.com 55911308Santhony.gutierrez@amd.com tcc_cntrl.probeFromNB = MessageBuffer() 56011308Santhony.gutierrez@amd.com tcc_cntrl.probeFromNB.slave = ruby_system.network.master 56111308Santhony.gutierrez@amd.com 56211308Santhony.gutierrez@amd.com tcc_cntrl.responseFromNB = MessageBuffer() 56311308Santhony.gutierrez@amd.com tcc_cntrl.responseFromNB.slave = ruby_system.network.master 56411308Santhony.gutierrez@amd.com 56511308Santhony.gutierrez@amd.com tcc_cntrl.requestToNB = MessageBuffer(ordered = True) 56611308Santhony.gutierrez@amd.com tcc_cntrl.requestToNB.master = ruby_system.network.slave 56711308Santhony.gutierrez@amd.com 56811308Santhony.gutierrez@amd.com tcc_cntrl.responseToNB = MessageBuffer() 56911308Santhony.gutierrez@amd.com tcc_cntrl.responseToNB.master = ruby_system.network.slave 57011308Santhony.gutierrez@amd.com 57111308Santhony.gutierrez@amd.com tcc_cntrl.unblockToNB = MessageBuffer() 57211308Santhony.gutierrez@amd.com tcc_cntrl.unblockToNB.master = ruby_system.network.slave 57311308Santhony.gutierrez@amd.com 57411308Santhony.gutierrez@amd.com tcc_cntrl.triggerQueue = MessageBuffer(ordered = True) 57511308Santhony.gutierrez@amd.com 57611308Santhony.gutierrez@amd.com exec("system.tcc_cntrl%d = tcc_cntrl" % i) 57711308Santhony.gutierrez@amd.com # connect all of the wire buffers between L3 and dirs up 57811308Santhony.gutierrez@amd.com # TCC cntrls added to the GPU cluster 57911308Santhony.gutierrez@amd.com gpuCluster.add(tcc_cntrl) 58011308Santhony.gutierrez@amd.com 58111308Santhony.gutierrez@amd.com # Assuming no DMA devices 58211308Santhony.gutierrez@amd.com assert(len(dma_devices) == 0) 58311308Santhony.gutierrez@amd.com 58411308Santhony.gutierrez@amd.com # Add cpu/gpu clusters to main cluster 58511308Santhony.gutierrez@amd.com mainCluster.add(cpuCluster) 58611308Santhony.gutierrez@amd.com mainCluster.add(gpuCluster) 58711308Santhony.gutierrez@amd.com 58811308Santhony.gutierrez@amd.com ruby_system.network.number_of_virtual_networks = 10 58911308Santhony.gutierrez@amd.com 59011308Santhony.gutierrez@amd.com return (cpu_sequencers, dir_cntrl_nodes, mainCluster) 591