simple_ruby.py revision 13980:62a28c423e91
12650Ssaidi@eecs.umich.edu# -*- coding: utf-8 -*- 22650Ssaidi@eecs.umich.edu# Copyright (c) 2015 Jason Power 32650Ssaidi@eecs.umich.edu# All rights reserved. 42650Ssaidi@eecs.umich.edu# 52650Ssaidi@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu# modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu# met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu# documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu# neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu# contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu# this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu# 162650Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu# 282665Ssaidi@eecs.umich.edu# Authors: Jason Lowe-Power 292650Ssaidi@eecs.umich.edu 302650Ssaidi@eecs.umich.edu""" This file creates a system with Ruby caches and executes 'threads', a 313817Ssaidi@eecs.umich.edusimple multi-threaded application with false sharing to stress the Ruby 323817Ssaidi@eecs.umich.eduprotocol. 333817Ssaidi@eecs.umich.edu 343817Ssaidi@eecs.umich.eduSee Part 3 in the Learning gem5 book: learning.gem5.org/book/part3 353817Ssaidi@eecs.umich.edu 362650Ssaidi@eecs.umich.eduIMPORTANT: If you modify this file, it's likely that the Learning gem5 book 373817Ssaidi@eecs.umich.edu also needs to be updated. For now, email Jason <jason@lowepower.com> 383817Ssaidi@eecs.umich.edu 393817Ssaidi@eecs.umich.edu""" 403817Ssaidi@eecs.umich.edufrom __future__ import print_function 412680Sktlim@umich.edufrom __future__ import absolute_import 422650Ssaidi@eecs.umich.edu 432650Ssaidi@eecs.umich.edu# import the m5 (gem5) library created when gem5 is built 442650Ssaidi@eecs.umich.eduimport m5 452982Sstever@eecs.umich.edu# import all of the SimObjects 462650Ssaidi@eecs.umich.edufrom m5.objects import * 472650Ssaidi@eecs.umich.edu 482650Ssaidi@eecs.umich.edu# Needed for running C++ threads 493827Shsul@eecs.umich.edum5.util.addToPath('../../') 503828Shsul@eecs.umich.edufrom common.FileSystemConfig import config_filesystem 513817Ssaidi@eecs.umich.edu 522650Ssaidi@eecs.umich.edu# You can import ruby_caches_MI_example to use the MI_example protocol instead 532650Ssaidi@eecs.umich.edu# of the MSI protocol 543891Ssaidi@eecs.umich.edufrom msi_caches import MyCacheSystem 552650Ssaidi@eecs.umich.edu 563891Ssaidi@eecs.umich.edu# create the system we are going to simulate 572650Ssaidi@eecs.umich.edusystem = System() 582650Ssaidi@eecs.umich.edu 592651Ssaidi@eecs.umich.edu# Set the clock fequency of the system (and all of its children) 602680Sktlim@umich.edusystem.clk_domain = SrcClockDomain() 612650Ssaidi@eecs.umich.edusystem.clk_domain.clock = '1GHz' 623817Ssaidi@eecs.umich.edusystem.clk_domain.voltage_domain = VoltageDomain() 633817Ssaidi@eecs.umich.edu 643817Ssaidi@eecs.umich.edu# Set up the system 653817Ssaidi@eecs.umich.edusystem.mem_mode = 'timing' # Use timing accesses 663817Ssaidi@eecs.umich.edusystem.mem_ranges = [AddrRange('512MB')] # Create an address range 673888Ssaidi@eecs.umich.edu 683817Ssaidi@eecs.umich.edu# Create a pair of simple CPUs 692650Ssaidi@eecs.umich.edusystem.cpu = [TimingSimpleCPU() for i in range(2)] 702650Ssaidi@eecs.umich.edu 712651Ssaidi@eecs.umich.edu# Create a DDR3 memory controller and connect it to the membus 722680Sktlim@umich.edusystem.mem_ctrl = DDR3_1600_8x8() 732650Ssaidi@eecs.umich.edusystem.mem_ctrl.range = system.mem_ranges[0] 743888Ssaidi@eecs.umich.edu 753817Ssaidi@eecs.umich.edu# create the interrupt controller for the CPU and connect to the membus 763890Ssaidi@eecs.umich.edufor cpu in system.cpu: 773888Ssaidi@eecs.umich.edu cpu.createInterruptController() 783817Ssaidi@eecs.umich.edu 793888Ssaidi@eecs.umich.edu# Create the Ruby System 803888Ssaidi@eecs.umich.edusystem.caches = MyCacheSystem() 813817Ssaidi@eecs.umich.edusystem.caches.setup(system, system.cpu, [system.mem_ctrl]) 822650Ssaidi@eecs.umich.edu 833827Shsul@eecs.umich.edu# get ISA for the binary to run. 843827Shsul@eecs.umich.eduisa = str(m5.defines.buildEnv['TARGET_ISA']).lower() 853827Shsul@eecs.umich.edu 863827Shsul@eecs.umich.edu# Run application and use the compiled ISA to find the binary 873827Shsul@eecs.umich.edu# grab the specific path to the binary 883827Shsul@eecs.umich.eduthispath = os.path.dirname(os.path.realpath(__file__)) 892650Ssaidi@eecs.umich.edubinary = os.path.join(thispath, '../../../', 'tests/test-progs/threads/bin/', 903827Shsul@eecs.umich.edu isa, 'linux/threads') 913827Shsul@eecs.umich.edu 923827Shsul@eecs.umich.edu# Create a process for a simple "multi-threaded" application 933817Ssaidi@eecs.umich.eduprocess = Process() 943817Ssaidi@eecs.umich.edu# Set the command 952650Ssaidi@eecs.umich.edu# cmd is a list which begins with the executable (like argv) 963817Ssaidi@eecs.umich.eduprocess.cmd = [binary] 973817Ssaidi@eecs.umich.edu# Set the cpu to use the process as its workload and create thread contexts 982650Ssaidi@eecs.umich.edufor cpu in system.cpu: 992650Ssaidi@eecs.umich.edu cpu.workload = process 1002650Ssaidi@eecs.umich.edu cpu.createThreads() 1012650Ssaidi@eecs.umich.edu 1023817Ssaidi@eecs.umich.edu# Set up the pseudo file system for the threads function above 1032650Ssaidi@eecs.umich.educonfig_filesystem(system) 1043828Shsul@eecs.umich.edu 1053828Shsul@eecs.umich.edu# set up the root SimObject and start the simulation 1063828Shsul@eecs.umich.eduroot = Root(full_system = False, system = system) 1073828Shsul@eecs.umich.edu# instantiate all of the objects we've created above 1083828Shsul@eecs.umich.edum5.instantiate() 1093828Shsul@eecs.umich.edu 1103828Shsul@eecs.umich.eduprint("Beginning simulation!") 1113828Shsul@eecs.umich.eduexit_event = m5.simulate() 1123828Shsul@eecs.umich.eduprint('Exiting @ tick {} because {}'.format( 1133828Shsul@eecs.umich.edu m5.curTick(), exit_event.getCause()) 1143828Shsul@eecs.umich.edu ) 1153828Shsul@eecs.umich.edu