simple_ruby.py revision 13840:b831620edab0
14166SN/A# -*- coding: utf-8 -*- 24166SN/A# Copyright (c) 2015 Jason Power 34166SN/A# All rights reserved. 44166SN/A# 57087SN/A# Redistribution and use in source and binary forms, with or without 67087SN/A# modification, are permitted provided that the following conditions are 77087SN/A# met: redistributions of source code must retain the above copyright 87087SN/A# notice, this list of conditions and the following disclaimer; 97087SN/A# redistributions in binary form must reproduce the above copyright 107087SN/A# notice, this list of conditions and the following disclaimer in the 117087SN/A# documentation and/or other materials provided with the distribution; 127087SN/A# neither the name of the copyright holders nor the names of its 134166SN/A# contributors may be used to endorse or promote products derived from 147087SN/A# this software without specific prior written permission. 157087SN/A# 167087SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177087SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187087SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197087SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207087SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217087SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224166SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237087SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244166SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254166SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264166SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274166SN/A# 284166SN/A# Authors: Jason Lowe-Power 294166SN/A 304166SN/A""" This file creates a system with Ruby caches and executes 'threads', a 314166SN/Asimple multi-threaded application with false sharing to stress the Ruby 324166SN/Aprotocol. 334166SN/A 344166SN/ASee Part 3 in the Learning gem5 book: learning.gem5.org/book/part3 354166SN/A 364166SN/AIMPORTANT: If you modify this file, it's likely that the Learning gem5 book 374166SN/A also needs to be updated. For now, email Jason <jason@lowepower.com> 384166SN/A 394166SN/A""" 404166SN/Afrom __future__ import print_function 414166SN/Afrom __future__ import absolute_import 424166SN/A 435063SN/A# import the m5 (gem5) library created when gem5 is built 444680SN/Aimport m5 4512334Sgabeblack@google.com# import all of the SimObjects 466359SN/Afrom m5.objects import * 474679SN/A 484166SN/A# You can import ruby_caches_MI_example to use the MI_example protocol instead 494166SN/A# of the MSI protocol 504679SN/Afrom msi_caches import MyCacheSystem 514679SN/A 525061SN/A# create the system we are going to simulate 534679SN/Asystem = System() 545061SN/A 554679SN/A# Set the clock fequency of the system (and all of its children) 565061SN/Asystem.clk_domain = SrcClockDomain() 574679SN/Asystem.clk_domain.clock = '1GHz' 585061SN/Asystem.clk_domain.voltage_domain = VoltageDomain() 594679SN/A 605061SN/A# Set up the system 614679SN/Asystem.mem_mode = 'timing' # Use timing accesses 624679SN/Asystem.mem_ranges = [AddrRange('512MB')] # Create an address range 634166SN/A 644166SN/A# Create a pair of simple CPUs 654166SN/Asystem.cpu = [TimingSimpleCPU() for i in range(2)] 664333SN/A 674333SN/A# Create a DDR3 memory controller and connect it to the membus 684333SN/Asystem.mem_ctrl = DDR3_1600_8x8() 694333SN/Asystem.mem_ctrl.range = system.mem_ranges[0] 704166SN/A 714333SN/A# create the interrupt controller for the CPU and connect to the membus 724333SN/Afor cpu in system.cpu: 734333SN/A cpu.createInterruptController() 744333SN/A 754166SN/A# Create the Ruby System 764333SN/Asystem.caches = MyCacheSystem() 774333SN/Asystem.caches.setup(system, system.cpu, [system.mem_ctrl]) 784333SN/A 794333SN/A# get ISA for the binary to run. 804166SN/Aisa = str(m5.defines.buildEnv['TARGET_ISA']).lower() 814333SN/A 824333SN/A# Run application and use the compiled ISA to find the binary 834333SN/A# grab the specific path to the binary 844333SN/Athispath = os.path.dirname(os.path.realpath(__file__)) 854166SN/Abinary = os.path.join(thispath, '../../../', 'tests/test-progs/threads/bin/', 864333SN/A isa, 'linux/threads') 874333SN/A 884333SN/A# Create a process for a simple "multi-threaded" application 894574SN/Aprocess = Process() 904333SN/A# Set the command 914166SN/A# cmd is a list which begins with the executable (like argv) 924333SN/Aprocess.cmd = [binary] 934333SN/A# Set the cpu to use the process as its workload and create thread contexts 944333SN/Afor cpu in system.cpu: 954574SN/A cpu.workload = process 964333SN/A cpu.createThreads() 974166SN/A 984333SN/A# set up the root SimObject and start the simulation 994333SN/Aroot = Root(full_system = False, system = system) 1004333SN/A# instantiate all of the objects we've created above 1014574SN/Am5.instantiate() 1024333SN/A 1034166SN/Aprint("Beginning simulation!") 1044333SN/Aexit_event = m5.simulate() 1054333SN/Aprint('Exiting @ tick {} because {}'.format( 1064333SN/A m5.curTick(), exit_event.getCause()) 1074574SN/A ) 1084333SN/A