simple_ruby.py revision 12609:72f3f62b4f38
112600Sodanrc@yahoo.com.br# -*- coding: utf-8 -*- 212600Sodanrc@yahoo.com.br# Copyright (c) 2015 Jason Power 312600Sodanrc@yahoo.com.br# All rights reserved. 412600Sodanrc@yahoo.com.br# 512600Sodanrc@yahoo.com.br# Redistribution and use in source and binary forms, with or without 612600Sodanrc@yahoo.com.br# modification, are permitted provided that the following conditions are 712600Sodanrc@yahoo.com.br# met: redistributions of source code must retain the above copyright 812600Sodanrc@yahoo.com.br# notice, this list of conditions and the following disclaimer; 912600Sodanrc@yahoo.com.br# redistributions in binary form must reproduce the above copyright 1012600Sodanrc@yahoo.com.br# notice, this list of conditions and the following disclaimer in the 1112600Sodanrc@yahoo.com.br# documentation and/or other materials provided with the distribution; 1212600Sodanrc@yahoo.com.br# neither the name of the copyright holders nor the names of its 1312600Sodanrc@yahoo.com.br# contributors may be used to endorse or promote products derived from 1412600Sodanrc@yahoo.com.br# this software without specific prior written permission. 1512600Sodanrc@yahoo.com.br# 1612600Sodanrc@yahoo.com.br# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712600Sodanrc@yahoo.com.br# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812600Sodanrc@yahoo.com.br# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912600Sodanrc@yahoo.com.br# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012600Sodanrc@yahoo.com.br# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112600Sodanrc@yahoo.com.br# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212600Sodanrc@yahoo.com.br# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312600Sodanrc@yahoo.com.br# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412600Sodanrc@yahoo.com.br# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512600Sodanrc@yahoo.com.br# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612600Sodanrc@yahoo.com.br# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712600Sodanrc@yahoo.com.br# 2812600Sodanrc@yahoo.com.br# Authors: Jason Lowe-Power 2912600Sodanrc@yahoo.com.br 3012600Sodanrc@yahoo.com.br""" This file creates a system with Ruby caches and executes 'threads', a 3112600Sodanrc@yahoo.com.brsimple multi-threaded application with false sharing to stress the Ruby 3212600Sodanrc@yahoo.com.brprotocol. 3312600Sodanrc@yahoo.com.br 3412600Sodanrc@yahoo.com.brSee Part 3 in the Learning gem5 book: learning.gem5.org/book/part3 3512634Sodanrc@yahoo.com.br 3612626Sodanrc@yahoo.com.brIMPORTANT: If you modify this file, it's likely that the Learning gem5 book 3712607Sodanrc@yahoo.com.br also needs to be updated. For now, email Jason <jason@lowepower.com> 3812628Sodanrc@yahoo.com.br 3912600Sodanrc@yahoo.com.br""" 4012601Sodanrc@yahoo.com.brfrom __future__ import print_function 4112600Sodanrc@yahoo.com.br 4212685Sodanrc@yahoo.com.br# import the m5 (gem5) library created when gem5 is built 4313221Sodanrc@yahoo.com.brimport m5 44# import all of the SimObjects 45from m5.objects import * 46 47from msi_caches import MyCacheSystem 48 49# create the system we are going to simulate 50system = System() 51 52# Set the clock fequency of the system (and all of its children) 53system.clk_domain = SrcClockDomain() 54system.clk_domain.clock = '1GHz' 55system.clk_domain.voltage_domain = VoltageDomain() 56 57# Set up the system 58system.mem_mode = 'timing' # Use timing accesses 59system.mem_ranges = [AddrRange('512MB')] # Create an address range 60 61# Create a pair of simple CPUs 62system.cpu = [TimingSimpleCPU() for i in range(2)] 63 64# Create a DDR3 memory controller and connect it to the membus 65system.mem_ctrl = DDR3_1600_8x8() 66system.mem_ctrl.range = system.mem_ranges[0] 67 68# create the interrupt controller for the CPU and connect to the membus 69for cpu in system.cpu: 70 cpu.createInterruptController() 71 72# Create the Ruby System 73system.caches = MyCacheSystem() 74system.caches.setup(system, system.cpu, [system.mem_ctrl]) 75 76# get ISA for the binary to run. 77isa = str(m5.defines.buildEnv['TARGET_ISA']).lower() 78 79# Run application and use the compiled ISA to find the binary 80binary = 'tests/test-progs/threads/bin/' + isa + '/linux/threads' 81 82# Create a process for a simple "multi-threaded" application 83process = Process() 84# Set the command 85# cmd is a list which begins with the executable (like argv) 86process.cmd = [binary] 87# Set the cpu to use the process as its workload and create thread contexts 88for cpu in system.cpu: 89 cpu.workload = process 90 cpu.createThreads() 91 92# set up the root SimObject and start the simulation 93root = Root(full_system = False, system = system) 94# instantiate all of the objects we've created above 95m5.instantiate() 96 97print("Beginning simulation!") 98exit_event = m5.simulate() 99print('Exiting @ tick {} because {}'.format( 100 m5.curTick(), exit_event.getCause()) 101 ) 102