simple_ruby.py revision 12611
112609Sjason@lowepower.com# -*- coding: utf-8 -*- 212609Sjason@lowepower.com# Copyright (c) 2015 Jason Power 312609Sjason@lowepower.com# All rights reserved. 412609Sjason@lowepower.com# 512609Sjason@lowepower.com# Redistribution and use in source and binary forms, with or without 612609Sjason@lowepower.com# modification, are permitted provided that the following conditions are 712609Sjason@lowepower.com# met: redistributions of source code must retain the above copyright 812609Sjason@lowepower.com# notice, this list of conditions and the following disclaimer; 912609Sjason@lowepower.com# redistributions in binary form must reproduce the above copyright 1012609Sjason@lowepower.com# notice, this list of conditions and the following disclaimer in the 1112609Sjason@lowepower.com# documentation and/or other materials provided with the distribution; 1212609Sjason@lowepower.com# neither the name of the copyright holders nor the names of its 1312609Sjason@lowepower.com# contributors may be used to endorse or promote products derived from 1412609Sjason@lowepower.com# this software without specific prior written permission. 1512609Sjason@lowepower.com# 1612609Sjason@lowepower.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712609Sjason@lowepower.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812609Sjason@lowepower.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912609Sjason@lowepower.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012609Sjason@lowepower.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112609Sjason@lowepower.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212609Sjason@lowepower.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312609Sjason@lowepower.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412609Sjason@lowepower.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512609Sjason@lowepower.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612609Sjason@lowepower.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712609Sjason@lowepower.com# 2812609Sjason@lowepower.com# Authors: Jason Lowe-Power 2912609Sjason@lowepower.com 3012609Sjason@lowepower.com""" This file creates a system with Ruby caches and executes 'threads', a 3112609Sjason@lowepower.comsimple multi-threaded application with false sharing to stress the Ruby 3212609Sjason@lowepower.comprotocol. 3312609Sjason@lowepower.com 3412609Sjason@lowepower.comSee Part 3 in the Learning gem5 book: learning.gem5.org/book/part3 3512609Sjason@lowepower.com 3612609Sjason@lowepower.comIMPORTANT: If you modify this file, it's likely that the Learning gem5 book 3712609Sjason@lowepower.com also needs to be updated. For now, email Jason <jason@lowepower.com> 3812609Sjason@lowepower.com 3912609Sjason@lowepower.com""" 4012609Sjason@lowepower.comfrom __future__ import print_function 4112609Sjason@lowepower.com 4212609Sjason@lowepower.com# import the m5 (gem5) library created when gem5 is built 4312609Sjason@lowepower.comimport m5 4412609Sjason@lowepower.com# import all of the SimObjects 4512609Sjason@lowepower.comfrom m5.objects import * 4612609Sjason@lowepower.com 4712611Sjason@lowepower.com# You can import ruby_caches_MI_example to use the MI_example protocol instead 4812611Sjason@lowepower.com# of the MSI protocol 4912609Sjason@lowepower.comfrom msi_caches import MyCacheSystem 5012609Sjason@lowepower.com 5112609Sjason@lowepower.com# create the system we are going to simulate 5212609Sjason@lowepower.comsystem = System() 5312609Sjason@lowepower.com 5412609Sjason@lowepower.com# Set the clock fequency of the system (and all of its children) 5512609Sjason@lowepower.comsystem.clk_domain = SrcClockDomain() 5612609Sjason@lowepower.comsystem.clk_domain.clock = '1GHz' 5712609Sjason@lowepower.comsystem.clk_domain.voltage_domain = VoltageDomain() 5812609Sjason@lowepower.com 5912609Sjason@lowepower.com# Set up the system 6012609Sjason@lowepower.comsystem.mem_mode = 'timing' # Use timing accesses 6112609Sjason@lowepower.comsystem.mem_ranges = [AddrRange('512MB')] # Create an address range 6212609Sjason@lowepower.com 6312609Sjason@lowepower.com# Create a pair of simple CPUs 6412609Sjason@lowepower.comsystem.cpu = [TimingSimpleCPU() for i in range(2)] 6512609Sjason@lowepower.com 6612609Sjason@lowepower.com# Create a DDR3 memory controller and connect it to the membus 6712609Sjason@lowepower.comsystem.mem_ctrl = DDR3_1600_8x8() 6812609Sjason@lowepower.comsystem.mem_ctrl.range = system.mem_ranges[0] 6912609Sjason@lowepower.com 7012609Sjason@lowepower.com# create the interrupt controller for the CPU and connect to the membus 7112609Sjason@lowepower.comfor cpu in system.cpu: 7212609Sjason@lowepower.com cpu.createInterruptController() 7312609Sjason@lowepower.com 7412609Sjason@lowepower.com# Create the Ruby System 7512609Sjason@lowepower.comsystem.caches = MyCacheSystem() 7612609Sjason@lowepower.comsystem.caches.setup(system, system.cpu, [system.mem_ctrl]) 7712609Sjason@lowepower.com 7812609Sjason@lowepower.com# get ISA for the binary to run. 7912609Sjason@lowepower.comisa = str(m5.defines.buildEnv['TARGET_ISA']).lower() 8012609Sjason@lowepower.com 8112609Sjason@lowepower.com# Run application and use the compiled ISA to find the binary 8212609Sjason@lowepower.combinary = 'tests/test-progs/threads/bin/' + isa + '/linux/threads' 8312609Sjason@lowepower.com 8412609Sjason@lowepower.com# Create a process for a simple "multi-threaded" application 8512609Sjason@lowepower.comprocess = Process() 8612609Sjason@lowepower.com# Set the command 8712609Sjason@lowepower.com# cmd is a list which begins with the executable (like argv) 8812609Sjason@lowepower.comprocess.cmd = [binary] 8912609Sjason@lowepower.com# Set the cpu to use the process as its workload and create thread contexts 9012609Sjason@lowepower.comfor cpu in system.cpu: 9112609Sjason@lowepower.com cpu.workload = process 9212609Sjason@lowepower.com cpu.createThreads() 9312609Sjason@lowepower.com 9412609Sjason@lowepower.com# set up the root SimObject and start the simulation 9512609Sjason@lowepower.comroot = Root(full_system = False, system = system) 9612609Sjason@lowepower.com# instantiate all of the objects we've created above 9712609Sjason@lowepower.comm5.instantiate() 9812609Sjason@lowepower.com 9912609Sjason@lowepower.comprint("Beginning simulation!") 10012609Sjason@lowepower.comexit_event = m5.simulate() 10112609Sjason@lowepower.comprint('Exiting @ tick {} because {}'.format( 10212609Sjason@lowepower.com m5.curTick(), exit_event.getCause()) 10312609Sjason@lowepower.com ) 104