ruby_test.py revision 13774:a1be2a0c55f2
11817SN/A# -*- coding: utf-8 -*- 21817SN/A# Copyright (c) 2015 Jason Power 31817SN/A# All rights reserved. 41817SN/A# 51817SN/A# Redistribution and use in source and binary forms, with or without 61817SN/A# modification, are permitted provided that the following conditions are 71817SN/A# met: redistributions of source code must retain the above copyright 81817SN/A# notice, this list of conditions and the following disclaimer; 91817SN/A# redistributions in binary form must reproduce the above copyright 101817SN/A# notice, this list of conditions and the following disclaimer in the 111817SN/A# documentation and/or other materials provided with the distribution; 121817SN/A# neither the name of the copyright holders nor the names of its 131817SN/A# contributors may be used to endorse or promote products derived from 141817SN/A# this software without specific prior written permission. 151817SN/A# 161817SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171817SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181817SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191817SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201817SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211817SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221817SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231817SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241817SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251817SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261817SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu# 283499Ssaidi@eecs.umich.edu# Authors: Jason Lowe-Power 291817SN/A 301817SN/A""" This file creates a system with Ruby caches and runs the ruby random tester 311817SN/ASee Part 3 in the Learning gem5 book: learning.gem5.org/book/part3 321817SN/A 331817SN/AIMPORTANT: If you modify this file, it's likely that the Learning gem5 book 341817SN/A also needs to be updated. For now, email Jason <jason@lowepower.com> 351817SN/A 362542SN/A""" 372542SN/Afrom __future__ import print_function 383348Sbinkertn@umich.edufrom __future__ import absolute_import 391817SN/A 401817SN/A# import the m5 (gem5) library created when gem5 is built 411817SN/Aimport m5 421817SN/A# import all of the SimObjects 432539SN/Afrom m5.objects import * 442539SN/A 451817SN/Afrom .test_caches import TestCacheSystem 464762Snate@binkert.org 473499Ssaidi@eecs.umich.edu# create the system we are going to simulate 483499Ssaidi@eecs.umich.edusystem = System() 494762Snate@binkert.org 504762Snate@binkert.org# Set the clock fequency of the system (and all of its children) 514762Snate@binkert.orgsystem.clk_domain = SrcClockDomain() 524762Snate@binkert.orgsystem.clk_domain.clock = '1GHz' 532539SN/Asystem.clk_domain.voltage_domain = VoltageDomain() 541817SN/A 552539SN/A# Set up the system 563349Sbinkertn@umich.edusystem.mem_mode = 'timing' # Use timing accesses 572539SN/Asystem.mem_ranges = [AddrRange('512MB')] # Create an address range 582539SN/A 594986Ssaidi@eecs.umich.edu# Create the tester 604762Snate@binkert.orgsystem.tester = RubyTester(checks_to_complete = 100, 613814Ssaidi@eecs.umich.edu wakeup_frequency = 10, 623814Ssaidi@eecs.umich.edu num_cpus = 2) 634762Snate@binkert.org 645192Ssaidi@eecs.umich.edu# Create a DDR3 memory controller and connect it to the membus 653499Ssaidi@eecs.umich.edusystem.mem_ctrl = DDR3_1600_8x8() 664870Sstever@eecs.umich.edusystem.mem_ctrl.range = system.mem_ranges[0] 673499Ssaidi@eecs.umich.edu 683499Ssaidi@eecs.umich.edu# Create the Ruby System 695192Ssaidi@eecs.umich.edusystem.caches = TestCacheSystem() 703499Ssaidi@eecs.umich.edusystem.caches.setup(system, system.tester, [system.mem_ctrl]) 713499Ssaidi@eecs.umich.edu 723499Ssaidi@eecs.umich.edu# set up the root SimObject and start the simulation 733814Ssaidi@eecs.umich.eduroot = Root(full_system = False, system = system) 743499Ssaidi@eecs.umich.edu 753499Ssaidi@eecs.umich.edu# Not much point in this being higher than the L1 latency 763814Ssaidi@eecs.umich.edum5.ticks.setGlobalFrequency('1ns') 773499Ssaidi@eecs.umich.edu 783499Ssaidi@eecs.umich.edu# instantiate all of the objects we've created above 793814Ssaidi@eecs.umich.edum5.instantiate() 803499Ssaidi@eecs.umich.edu 813499Ssaidi@eecs.umich.eduprint("Beginning simulation!") 823814Ssaidi@eecs.umich.eduexit_event = m5.simulate() 833499Ssaidi@eecs.umich.eduprint('Exiting @ tick {} because {}'.format( 843499Ssaidi@eecs.umich.edu m5.curTick(), exit_event.getCause()) 853499Ssaidi@eecs.umich.edu ) 863499Ssaidi@eecs.umich.edu