simple_cache.py revision 13839
112339Sjason@lowepower.com# -*- coding: utf-8 -*- 212339Sjason@lowepower.com# Copyright (c) 2017 Jason Lowe-Power 312339Sjason@lowepower.com# All rights reserved. 412339Sjason@lowepower.com# 512339Sjason@lowepower.com# Redistribution and use in source and binary forms, with or without 612339Sjason@lowepower.com# modification, are permitted provided that the following conditions are 712339Sjason@lowepower.com# met: redistributions of source code must retain the above copyright 812339Sjason@lowepower.com# notice, this list of conditions and the following disclaimer; 912339Sjason@lowepower.com# redistributions in binary form must reproduce the above copyright 1012339Sjason@lowepower.com# notice, this list of conditions and the following disclaimer in the 1112339Sjason@lowepower.com# documentation and/or other materials provided with the distribution; 1212339Sjason@lowepower.com# neither the name of the copyright holders nor the names of its 1312339Sjason@lowepower.com# contributors may be used to endorse or promote products derived from 1412339Sjason@lowepower.com# this software without specific prior written permission. 1512339Sjason@lowepower.com# 1612339Sjason@lowepower.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712339Sjason@lowepower.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812339Sjason@lowepower.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912339Sjason@lowepower.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012339Sjason@lowepower.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112339Sjason@lowepower.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212339Sjason@lowepower.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312339Sjason@lowepower.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412339Sjason@lowepower.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512339Sjason@lowepower.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612339Sjason@lowepower.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712339Sjason@lowepower.com# 2812339Sjason@lowepower.com# Authors: Jason Lowe-Power 2912339Sjason@lowepower.com 3012339Sjason@lowepower.com""" This file creates a barebones system and executes 'hello', a simple Hello 3112339Sjason@lowepower.comWorld application. Adds a simple cache between the CPU and the membus. 3212339Sjason@lowepower.com 3312339Sjason@lowepower.comThis config file assumes that the x86 ISA was built. 3412339Sjason@lowepower.com""" 3512339Sjason@lowepower.com 3612564Sgabeblack@google.comfrom __future__ import print_function 3713774Sandreas.sandberg@arm.comfrom __future__ import absolute_import 3812564Sgabeblack@google.com 3912339Sjason@lowepower.com# import the m5 (gem5) library created when gem5 is built 4012339Sjason@lowepower.comimport m5 4112339Sjason@lowepower.com# import all of the SimObjects 4212339Sjason@lowepower.comfrom m5.objects import * 4312339Sjason@lowepower.com 4412339Sjason@lowepower.com# create the system we are going to simulate 4512339Sjason@lowepower.comsystem = System() 4612339Sjason@lowepower.com 4712339Sjason@lowepower.com# Set the clock fequency of the system (and all of its children) 4812339Sjason@lowepower.comsystem.clk_domain = SrcClockDomain() 4912339Sjason@lowepower.comsystem.clk_domain.clock = '1GHz' 5012339Sjason@lowepower.comsystem.clk_domain.voltage_domain = VoltageDomain() 5112339Sjason@lowepower.com 5212339Sjason@lowepower.com# Set up the system 5312339Sjason@lowepower.comsystem.mem_mode = 'timing' # Use timing accesses 5412339Sjason@lowepower.comsystem.mem_ranges = [AddrRange('512MB')] # Create an address range 5512339Sjason@lowepower.com 5612339Sjason@lowepower.com# Create a simple CPU 5712339Sjason@lowepower.comsystem.cpu = TimingSimpleCPU() 5812339Sjason@lowepower.com 5912339Sjason@lowepower.com# Create a memory bus, a coherent crossbar, in this case 6012339Sjason@lowepower.comsystem.membus = SystemXBar() 6112339Sjason@lowepower.com 6212339Sjason@lowepower.com# Create a simple cache 6312339Sjason@lowepower.comsystem.cache = SimpleCache(size='1kB') 6412339Sjason@lowepower.com 6512339Sjason@lowepower.com# Connect the I and D cache ports of the CPU to the memobj. 6612339Sjason@lowepower.com# Since cpu_side is a vector port, each time one of these is connected, it will 6712339Sjason@lowepower.com# create a new instance of the CPUSidePort class 6812339Sjason@lowepower.comsystem.cpu.icache_port = system.cache.cpu_side 6912339Sjason@lowepower.comsystem.cpu.dcache_port = system.cache.cpu_side 7012339Sjason@lowepower.com 7112339Sjason@lowepower.com# Hook the cache up to the memory bus 7212339Sjason@lowepower.comsystem.cache.mem_side = system.membus.slave 7312339Sjason@lowepower.com 7412339Sjason@lowepower.com# create the interrupt controller for the CPU and connect to the membus 7512339Sjason@lowepower.comsystem.cpu.createInterruptController() 7612339Sjason@lowepower.comsystem.cpu.interrupts[0].pio = system.membus.master 7712339Sjason@lowepower.comsystem.cpu.interrupts[0].int_master = system.membus.slave 7812339Sjason@lowepower.comsystem.cpu.interrupts[0].int_slave = system.membus.master 7912339Sjason@lowepower.com 8012339Sjason@lowepower.com# Create a DDR3 memory controller and connect it to the membus 8112339Sjason@lowepower.comsystem.mem_ctrl = DDR3_1600_8x8() 8212339Sjason@lowepower.comsystem.mem_ctrl.range = system.mem_ranges[0] 8312339Sjason@lowepower.comsystem.mem_ctrl.port = system.membus.master 8412339Sjason@lowepower.com 8512339Sjason@lowepower.com# Connect the system up to the membus 8612339Sjason@lowepower.comsystem.system_port = system.membus.slave 8712339Sjason@lowepower.com 8812339Sjason@lowepower.com# Create a process for a simple "Hello World" application 8912339Sjason@lowepower.comprocess = Process() 9012339Sjason@lowepower.com# Set the command 9113839Sjason@lowepower.com# grab the specific path to the binary 9213839Sjason@lowepower.comthispath = os.path.dirname(os.path.realpath(__file__)) 9313839Sjason@lowepower.combinpath = os.path.join(thispath, '../../../', 9413839Sjason@lowepower.com 'tests/test-progs/hello/bin/x86/linux/hello') 9512339Sjason@lowepower.com# cmd is a list which begins with the executable (like argv) 9613839Sjason@lowepower.comprocess.cmd = [binpath] 9712339Sjason@lowepower.com# Set the cpu to use the process as its workload and create thread contexts 9812339Sjason@lowepower.comsystem.cpu.workload = process 9912339Sjason@lowepower.comsystem.cpu.createThreads() 10012339Sjason@lowepower.com 10112339Sjason@lowepower.com# set up the root SimObject and start the simulation 10212339Sjason@lowepower.comroot = Root(full_system = False, system = system) 10312339Sjason@lowepower.com# instantiate all of the objects we've created above 10412339Sjason@lowepower.comm5.instantiate() 10512339Sjason@lowepower.com 10612564Sgabeblack@google.comprint("Beginning simulation!") 10712339Sjason@lowepower.comexit_event = m5.simulate() 10812564Sgabeblack@google.comprint('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())) 109