simple_cache.py revision 12339
12SN/A# -*- coding: utf-8 -*- 22188SN/A# Copyright (c) 2017 Jason Lowe-Power 32SN/A# All rights reserved. 42SN/A# 52SN/A# Redistribution and use in source and binary forms, with or without 62SN/A# modification, are permitted provided that the following conditions are 72SN/A# met: redistributions of source code must retain the above copyright 82SN/A# notice, this list of conditions and the following disclaimer; 92SN/A# redistributions in binary form must reproduce the above copyright 102SN/A# notice, this list of conditions and the following disclaimer in the 112SN/A# documentation and/or other materials provided with the distribution; 122SN/A# neither the name of the copyright holders nor the names of its 132SN/A# contributors may be used to endorse or promote products derived from 142SN/A# this software without specific prior written permission. 152SN/A# 162SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A# 282665SN/A# Authors: Jason Lowe-Power 292665SN/A 302665SN/A""" This file creates a barebones system and executes 'hello', a simple Hello 312665SN/AWorld application. Adds a simple cache between the CPU and the membus. 322SN/A 332SN/AThis config file assumes that the x86 ISA was built. 342SN/A""" 352SN/A 362465SN/A# import the m5 (gem5) library created when gem5 is built 371717SN/Aimport m5 382683Sktlim@umich.edu# import all of the SimObjects 392680SN/Afrom m5.objects import * 402SN/A 411858SN/A# create the system we are going to simulate 423565Sgblack@eecs.umich.edusystem = System() 431917SN/A 441070SN/A# Set the clock fequency of the system (and all of its children) 451917SN/Asystem.clk_domain = SrcClockDomain() 462188SN/Asystem.clk_domain.clock = '1GHz' 471917SN/Asystem.clk_domain.voltage_domain = VoltageDomain() 482290SN/A 491070SN/A# Set up the system 501917SN/Asystem.mem_mode = 'timing' # Use timing accesses 512170SN/Asystem.mem_ranges = [AddrRange('512MB')] # Create an address range 522SN/A 53360SN/A# Create a simple CPU 542519SN/Asystem.cpu = TimingSimpleCPU() 552420SN/A 562SN/A# Create a memory bus, a coherent crossbar, in this case 572SN/Asystem.membus = SystemXBar() 582SN/A 592SN/A# Create a simple cache 602SN/Asystem.cache = SimpleCache(size='1kB') 611858SN/A 622683Sktlim@umich.edu# Connect the I and D cache ports of the CPU to the memobj. 633453Sgblack@eecs.umich.edu# Since cpu_side is a vector port, each time one of these is connected, it will 642683Sktlim@umich.edu# create a new instance of the CPUSidePort class 653402Sktlim@umich.edusystem.cpu.icache_port = system.cache.cpu_side 662683Sktlim@umich.edusystem.cpu.dcache_port = system.cache.cpu_side 672521SN/A 682SN/A# Hook the cache up to the memory bus 692683Sktlim@umich.edusystem.cache.mem_side = system.membus.slave 702190SN/A 712680SN/A# create the interrupt controller for the CPU and connect to the membus 722290SN/Asystem.cpu.createInterruptController() 732526SN/Asystem.cpu.interrupts[0].pio = system.membus.master 741917SN/Asystem.cpu.interrupts[0].int_master = system.membus.slave 751917SN/Asystem.cpu.interrupts[0].int_slave = system.membus.master 761982SN/A 771917SN/A# Create a DDR3 memory controller and connect it to the membus 782683Sktlim@umich.edusystem.mem_ctrl = DDR3_1600_8x8() 792683Sktlim@umich.edusystem.mem_ctrl.range = system.mem_ranges[0] 801917SN/Asystem.mem_ctrl.port = system.membus.master 811917SN/A 821917SN/A# Connect the system up to the membus 831917SN/Asystem.system_port = system.membus.slave 841917SN/A 851917SN/A# Create a process for a simple "Hello World" application 861917SN/Aprocess = Process() 871917SN/A# Set the command 882521SN/A# cmd is a list which begins with the executable (like argv) 895482Snate@binkert.orgprocess.cmd = ['tests/test-progs/hello/bin/x86/linux/hello'] 903548Sgblack@eecs.umich.edu# Set the cpu to use the process as its workload and create thread contexts 912SN/Asystem.cpu.workload = process 922SN/Asystem.cpu.createThreads() 934997Sgblack@eecs.umich.edu 944997Sgblack@eecs.umich.edu# set up the root SimObject and start the simulation 953402Sktlim@umich.eduroot = Root(full_system = False, system = system) 964997Sgblack@eecs.umich.edu# instantiate all of the objects we've created above 972SN/Am5.instantiate() 982526SN/A 992683Sktlim@umich.eduprint "Beginning simulation!" 1002SN/Aexit_event = m5.simulate() 1012190SN/Aprint 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) 1022862Sktlim@umich.edu