simple.py revision 13839
12623SN/A# -*- coding: utf-8 -*- 22623SN/A# Copyright (c) 2015 Jason Power 32623SN/A# All rights reserved. 42623SN/A# 52623SN/A# Redistribution and use in source and binary forms, with or without 62623SN/A# modification, are permitted provided that the following conditions are 72623SN/A# met: redistributions of source code must retain the above copyright 82623SN/A# notice, this list of conditions and the following disclaimer; 92623SN/A# redistributions in binary form must reproduce the above copyright 102623SN/A# notice, this list of conditions and the following disclaimer in the 112623SN/A# documentation and/or other materials provided with the distribution; 122623SN/A# neither the name of the copyright holders nor the names of its 132623SN/A# contributors may be used to endorse or promote products derived from 142623SN/A# this software without specific prior written permission. 152623SN/A# 162623SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu# 282665Ssaidi@eecs.umich.edu# Authors: Jason Power 292623SN/A 302623SN/A""" This file creates a barebones system and executes 'hello', a simple Hello 312623SN/AWorld application. 322623SN/ASee Part 1, Chapter 2: Creating a simple configuration script in the 332623SN/Alearning_gem5 book for more information about this script. 342623SN/A 355529Snate@binkert.orgIMPORTANT: If you modify this file, it's likely that the Learning gem5 book 362623SN/A also needs to be updated. For now, email Jason <power.jg@gmail.com> 372623SN/A 382623SN/A""" 392623SN/A 402623SN/Afrom __future__ import print_function 415529Snate@binkert.orgfrom __future__ import absolute_import 422623SN/A 432623SN/A 442623SN/A# import the m5 (gem5) library created when gem5 is built 452623SN/Aimport m5 462623SN/A# import all of the SimObjects 472623SN/Afrom m5.objects import * 482623SN/A 492623SN/A# create the system we are going to simulate 502623SN/Asystem = System() 512623SN/A 522623SN/A# Set the clock fequency of the system (and all of its children) 532623SN/Asystem.clk_domain = SrcClockDomain() 545336Shines@cs.fsu.edusystem.clk_domain.clock = '1GHz' 552623SN/Asystem.clk_domain.voltage_domain = VoltageDomain() 562623SN/A 572623SN/A# Set up the system 582623SN/Asystem.mem_mode = 'timing' # Use timing accesses 592623SN/Asystem.mem_ranges = [AddrRange('512MB')] # Create an address range 605487Snate@binkert.org 615487Snate@binkert.org# Create a simple CPU 622623SN/Asystem.cpu = TimingSimpleCPU() 632623SN/A 642623SN/A# Create a memory bus, a system crossbar, in this case 652623SN/Asystem.membus = SystemXBar() 662623SN/A 672623SN/A# Hook the CPU ports up to the membus 682623SN/Asystem.cpu.icache_port = system.membus.slave 692623SN/Asystem.cpu.dcache_port = system.membus.slave 702640Sstever@eecs.umich.edu 713401Sktlim@umich.edu# create the interrupt controller for the CPU and connect to the membus 722623SN/Asystem.cpu.createInterruptController() 732623SN/A 743647Srdreslin@umich.edu# For x86 only, make sure the interrupts are connected to the memory 753647Srdreslin@umich.edu# Note: these are directly connected to the memory bus and are not cached 762623SN/Aif m5.defines.buildEnv['TARGET_ISA'] == "x86": 772623SN/A system.cpu.interrupts[0].pio = system.membus.master 784192Sktlim@umich.edu system.cpu.interrupts[0].int_master = system.membus.slave 794192Sktlim@umich.edu system.cpu.interrupts[0].int_slave = system.membus.master 803349Sbinkertn@umich.edu 812623SN/A# Create a DDR3 memory controller and connect it to the membus 823349Sbinkertn@umich.edusystem.mem_ctrl = DDR3_1600_8x8() 832623SN/Asystem.mem_ctrl.range = system.mem_ranges[0] 843349Sbinkertn@umich.edusystem.mem_ctrl.port = system.membus.master 852623SN/A 862623SN/A# Connect the system up to the membus 872623SN/Asystem.system_port = system.membus.slave 882657Ssaidi@eecs.umich.edu 892623SN/A# get ISA for the binary to run. 902623SN/Aisa = str(m5.defines.buildEnv['TARGET_ISA']).lower() 914475Sstever@eecs.umich.edu 924475Sstever@eecs.umich.edu# Default to running 'hello', use the compiled ISA to find the binary 933192Srdreslin@umich.edu# grab the specific path to the binary 942623SN/Athispath = os.path.dirname(os.path.realpath(__file__)) 952623SN/Abinary = os.path.join(thispath, '../../../', 964192Sktlim@umich.edu 'tests/test-progs/hello/bin/', isa, 'linux/hello') 974192Sktlim@umich.edu 984192Sktlim@umich.edu# Create a process for a simple "Hello World" application 994192Sktlim@umich.eduprocess = Process() 1004192Sktlim@umich.edu# Set the command 1014192Sktlim@umich.edu# cmd is a list which begins with the executable (like argv) 1024192Sktlim@umich.eduprocess.cmd = [binary] 1034192Sktlim@umich.edu# Set the cpu to use the process as its workload and create thread contexts 1044192Sktlim@umich.edusystem.cpu.workload = process 1054192Sktlim@umich.edusystem.cpu.createThreads() 1064192Sktlim@umich.edu 1072623SN/A# set up the root SimObject and start the simulation 1084968Sacolyte@umich.eduroot = Root(full_system = False, system = system) 1094968Sacolyte@umich.edu# instantiate all of the objects we've created above 1104870Sstever@eecs.umich.edum5.instantiate() 1114870Sstever@eecs.umich.edu 1124870Sstever@eecs.umich.eduprint("Beginning simulation!") 1132623SN/Aexit_event = m5.simulate() 1142623SN/Aprint('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())) 1152662Sstever@eecs.umich.edu