simple.py revision 11851
111104Spower.jg@gmail.com# -*- coding: utf-8 -*-
211104Spower.jg@gmail.com# Copyright (c) 2015 Jason Power
311104Spower.jg@gmail.com# All rights reserved.
411104Spower.jg@gmail.com#
511104Spower.jg@gmail.com# Redistribution and use in source and binary forms, with or without
611104Spower.jg@gmail.com# modification, are permitted provided that the following conditions are
711104Spower.jg@gmail.com# met: redistributions of source code must retain the above copyright
811104Spower.jg@gmail.com# notice, this list of conditions and the following disclaimer;
911104Spower.jg@gmail.com# redistributions in binary form must reproduce the above copyright
1011104Spower.jg@gmail.com# notice, this list of conditions and the following disclaimer in the
1111104Spower.jg@gmail.com# documentation and/or other materials provided with the distribution;
1211104Spower.jg@gmail.com# neither the name of the copyright holders nor the names of its
1311104Spower.jg@gmail.com# contributors may be used to endorse or promote products derived from
1411104Spower.jg@gmail.com# this software without specific prior written permission.
1511104Spower.jg@gmail.com#
1611104Spower.jg@gmail.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1711104Spower.jg@gmail.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1811104Spower.jg@gmail.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1911104Spower.jg@gmail.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2011104Spower.jg@gmail.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2111104Spower.jg@gmail.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2211104Spower.jg@gmail.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2311104Spower.jg@gmail.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2411104Spower.jg@gmail.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2511104Spower.jg@gmail.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2611104Spower.jg@gmail.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2711104Spower.jg@gmail.com#
2811104Spower.jg@gmail.com# Authors: Jason Power
2911104Spower.jg@gmail.com
3011104Spower.jg@gmail.com""" This file creates a barebones system and executes 'hello', a simple Hello
3111104Spower.jg@gmail.comWorld application.
3211104Spower.jg@gmail.comSee Part 1, Chapter 2: Creating a simple configuration script in the
3311104Spower.jg@gmail.comlearning_gem5 book for more information about this script.
3411104Spower.jg@gmail.com
3511104Spower.jg@gmail.comIMPORTANT: If you modify this file, it's likely that the Learning gem5 book
3611104Spower.jg@gmail.com           also needs to be updated. For now, email Jason <power.jg@gmail.com>
3711104Spower.jg@gmail.com
3811104Spower.jg@gmail.com"""
3911104Spower.jg@gmail.com
4011104Spower.jg@gmail.com# import the m5 (gem5) library created when gem5 is built
4111104Spower.jg@gmail.comimport m5
4211104Spower.jg@gmail.com# import all of the SimObjects
4311104Spower.jg@gmail.comfrom m5.objects import *
4411104Spower.jg@gmail.com
4511104Spower.jg@gmail.com# create the system we are going to simulate
4611104Spower.jg@gmail.comsystem = System()
4711104Spower.jg@gmail.com
4811104Spower.jg@gmail.com# Set the clock fequency of the system (and all of its children)
4911104Spower.jg@gmail.comsystem.clk_domain = SrcClockDomain()
5011104Spower.jg@gmail.comsystem.clk_domain.clock = '1GHz'
5111104Spower.jg@gmail.comsystem.clk_domain.voltage_domain = VoltageDomain()
5211104Spower.jg@gmail.com
5311104Spower.jg@gmail.com# Set up the system
5411104Spower.jg@gmail.comsystem.mem_mode = 'timing'               # Use timing accesses
5511104Spower.jg@gmail.comsystem.mem_ranges = [AddrRange('512MB')] # Create an address range
5611104Spower.jg@gmail.com
5711104Spower.jg@gmail.com# Create a simple CPU
5811104Spower.jg@gmail.comsystem.cpu = TimingSimpleCPU()
5911104Spower.jg@gmail.com
6011104Spower.jg@gmail.com# Create a memory bus, a system crossbar, in this case
6111104Spower.jg@gmail.comsystem.membus = SystemXBar()
6211104Spower.jg@gmail.com
6311104Spower.jg@gmail.com# Hook the CPU ports up to the membus
6411104Spower.jg@gmail.comsystem.cpu.icache_port = system.membus.slave
6511104Spower.jg@gmail.comsystem.cpu.dcache_port = system.membus.slave
6611104Spower.jg@gmail.com
6711104Spower.jg@gmail.com# create the interrupt controller for the CPU and connect to the membus
6811104Spower.jg@gmail.comsystem.cpu.createInterruptController()
6911104Spower.jg@gmail.com
7011104Spower.jg@gmail.com# For x86 only, make sure the interrupts are connected to the memory
7111104Spower.jg@gmail.com# Note: these are directly connected to the memory bus and are not cached
7211104Spower.jg@gmail.comif m5.defines.buildEnv['TARGET_ISA'] == "x86":
7311154Sandreas.hansson@arm.com    system.cpu.interrupts[0].pio = system.membus.master
7411154Sandreas.hansson@arm.com    system.cpu.interrupts[0].int_master = system.membus.slave
7511154Sandreas.hansson@arm.com    system.cpu.interrupts[0].int_slave = system.membus.master
7611104Spower.jg@gmail.com
7711104Spower.jg@gmail.com# Create a DDR3 memory controller and connect it to the membus
7811837Swendy.elsasser@arm.comsystem.mem_ctrl = DDR3_1600_8x8()
7911104Spower.jg@gmail.comsystem.mem_ctrl.range = system.mem_ranges[0]
8011104Spower.jg@gmail.comsystem.mem_ctrl.port = system.membus.master
8111104Spower.jg@gmail.com
8211104Spower.jg@gmail.com# Connect the system up to the membus
8311104Spower.jg@gmail.comsystem.system_port = system.membus.slave
8411104Spower.jg@gmail.com
8511104Spower.jg@gmail.com# get ISA for the binary to run.
8611104Spower.jg@gmail.comisa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
8711104Spower.jg@gmail.com
8811104Spower.jg@gmail.com# Run 'hello' and use the compiled ISA to find the binary
8911104Spower.jg@gmail.combinary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello'
9011104Spower.jg@gmail.com
9111104Spower.jg@gmail.com# Create a process for a simple "Hello World" application
9211851Sbrandon.potter@amd.comprocess = Process()
9311104Spower.jg@gmail.com# Set the command
9411104Spower.jg@gmail.com# cmd is a list which begins with the executable (like argv)
9511104Spower.jg@gmail.comprocess.cmd = [binary]
9611104Spower.jg@gmail.com# Set the cpu to use the process as its workload and create thread contexts
9711104Spower.jg@gmail.comsystem.cpu.workload = process
9811104Spower.jg@gmail.comsystem.cpu.createThreads()
9911104Spower.jg@gmail.com
10011104Spower.jg@gmail.com# set up the root SimObject and start the simulation
10111104Spower.jg@gmail.comroot = Root(full_system = False, system = system)
10211104Spower.jg@gmail.com# instantiate all of the objects we've created above
10311104Spower.jg@gmail.comm5.instantiate()
10411104Spower.jg@gmail.com
10511104Spower.jg@gmail.comprint "Beginning simulation!"
10611104Spower.jg@gmail.comexit_event = m5.simulate()
10711104Spower.jg@gmail.comprint 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
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