caches.py revision 12072:2ee7f25dd00d 
1# -*- coding: utf-8 -*-
2# Copyright (c) 2015 Jason Power
3# All rights reserved.
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27#
28# Authors: Jason Power
29
30""" Caches with options for a simple gem5 configuration script
31
32This file contains L1 I/D and L2 caches to be used in the simple
33gem5 configuration script. It uses the SimpleOpts wrapper to set up command
34line options from each individual class.
35"""
36import m5
37from m5.objects import Cache
38
39# Add the common scripts to our path
40m5.util.addToPath('../../')
41
42from common import SimpleOpts
43
44# Some specific options for caches
45# For all options see src/mem/cache/BaseCache.py
46
47class L1Cache(Cache):
48    """Simple L1 Cache with default values"""
49
50    assoc = 2
51    tag_latency = 2
52    data_latency = 2
53    response_latency = 2
54    mshrs = 4
55    tgts_per_mshr = 20
56
57    def __init__(self, options=None):
58        super(L1Cache, self).__init__()
59        pass
60
61    def connectBus(self, bus):
62        """Connect this cache to a memory-side bus"""
63        self.mem_side = bus.slave
64
65    def connectCPU(self, cpu):
66        """Connect this cache's port to a CPU-side port
67           This must be defined in a subclass"""
68        raise NotImplementedError
69
70class L1ICache(L1Cache):
71    """Simple L1 instruction cache with default values"""
72
73    # Set the default size
74    size = '16kB'
75
76    SimpleOpts.add_option('--l1i_size',
77                          help="L1 instruction cache size. Default: %s" % size)
78
79    def __init__(self, opts=None):
80        super(L1ICache, self).__init__(opts)
81        if not opts or not opts.l1i_size:
82            return
83        self.size = opts.l1i_size
84
85    def connectCPU(self, cpu):
86        """Connect this cache's port to a CPU icache port"""
87        self.cpu_side = cpu.icache_port
88
89class L1DCache(L1Cache):
90    """Simple L1 data cache with default values"""
91
92    # Set the default size
93    size = '64kB'
94
95    SimpleOpts.add_option('--l1d_size',
96                          help="L1 data cache size. Default: %s" % size)
97
98    def __init__(self, opts=None):
99        super(L1DCache, self).__init__(opts)
100        if not opts or not opts.l1d_size:
101            return
102        self.size = opts.l1d_size
103
104    def connectCPU(self, cpu):
105        """Connect this cache's port to a CPU dcache port"""
106        self.cpu_side = cpu.dcache_port
107
108class L2Cache(Cache):
109    """Simple L2 Cache with default values"""
110
111    # Default parameters
112    size = '256kB'
113    assoc = 8
114    tag_latency = 20
115    data_latency = 20
116    response_latency = 20
117    mshrs = 20
118    tgts_per_mshr = 12
119
120    SimpleOpts.add_option('--l2_size', help="L2 cache size. Default: %s" % size)
121
122    def __init__(self, opts=None):
123        super(L2Cache, self).__init__()
124        if not opts or not opts.l2_size:
125            return
126        self.size = opts.l2_size
127
128    def connectCPUSideBus(self, bus):
129        self.cpu_side = bus.master
130
131    def connectMemSideBus(self, bus):
132        self.mem_side = bus.slave
133