caches.py revision 11682:612f75cf36a0 
1# -*- coding: utf-8 -*-
2# Copyright (c) 2015 Jason Power
3# All rights reserved.
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28# Authors: Jason Power
29
30""" Caches with options for a simple gem5 configuration script
31
32This file contains L1 I/D and L2 caches to be used in the simple
33gem5 configuration script. It uses the SimpleOpts wrapper to set up command
34line options from each individual class.
35"""
36
37from m5.objects import Cache
38
39from common import SimpleOpts
40
41# Some specific options for caches
42# For all options see src/mem/cache/BaseCache.py
43
44class L1Cache(Cache):
45    """Simple L1 Cache with default values"""
46
47    assoc = 2
48    hit_latency = 2
49    response_latency = 2
50    mshrs = 4
51    tgts_per_mshr = 20
52
53    def __init__(self, options=None):
54        super(L1Cache, self).__init__()
55        pass
56
57    def connectBus(self, bus):
58        """Connect this cache to a memory-side bus"""
59        self.mem_side = bus.slave
60
61    def connectCPU(self, cpu):
62        """Connect this cache's port to a CPU-side port
63           This must be defined in a subclass"""
64        raise NotImplementedError
65
66class L1ICache(L1Cache):
67    """Simple L1 instruction cache with default values"""
68
69    # Set the default size
70    size = '16kB'
71
72    SimpleOpts.add_option('--l1i_size',
73                          help="L1 instruction cache size. Default: %s" % size)
74
75    def __init__(self, opts=None):
76        super(L1ICache, self).__init__(opts)
77        if not opts or not opts.l1i_size:
78            return
79        self.size = opts.l1i_size
80
81    def connectCPU(self, cpu):
82        """Connect this cache's port to a CPU icache port"""
83        self.cpu_side = cpu.icache_port
84
85class L1DCache(L1Cache):
86    """Simple L1 data cache with default values"""
87
88    # Set the default size
89    size = '64kB'
90
91    SimpleOpts.add_option('--l1d_size',
92                          help="L1 data cache size. Default: %s" % size)
93
94    def __init__(self, opts=None):
95        super(L1DCache, self).__init__(opts)
96        if not opts or not opts.l1d_size:
97            return
98        self.size = opts.l1d_size
99
100    def connectCPU(self, cpu):
101        """Connect this cache's port to a CPU dcache port"""
102        self.cpu_side = cpu.dcache_port
103
104class L2Cache(Cache):
105    """Simple L2 Cache with default values"""
106
107    # Default parameters
108    size = '256kB'
109    assoc = 8
110    hit_latency = 20
111    response_latency = 20
112    mshrs = 20
113    tgts_per_mshr = 12
114
115    SimpleOpts.add_option('--l2_size', help="L2 cache size. Default: %s" % size)
116
117    def __init__(self, opts=None):
118        super(L2Cache, self).__init__()
119        if not opts or not opts.l2_size:
120            return
121        self.size = opts.l2_size
122
123    def connectCPUSideBus(self, bus):
124        self.cpu_side = bus.master
125
126    def connectMemSideBus(self, bus):
127        self.mem_side = bus.slave
128