se.py revision 9907 
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
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13# Copyright (c) 2006-2008 The Regents of The University of Michigan
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38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47import os
48
49import m5
50from m5.defines import buildEnv
51from m5.objects import *
52from m5.util import addToPath, fatal
53
54addToPath('../common')
55addToPath('../ruby')
56addToPath('../topologies')
57
58import Options
59import Ruby
60import Simulation
61import CacheConfig
62import MemConfig
63from Caches import *
64from cpu2000 import *
65
66def get_processes(options):
67    """Interprets provided options and returns a list of processes"""
68
69    multiprocesses = []
70    inputs = []
71    outputs = []
72    errouts = []
73    pargs = []
74
75    workloads = options.cmd.split(';')
76    if options.input != "":
77        inputs = options.input.split(';')
78    if options.output != "":
79        outputs = options.output.split(';')
80    if options.errout != "":
81        errouts = options.errout.split(';')
82    if options.options != "":
83        pargs = options.options.split(';')
84
85    idx = 0
86    for wrkld in workloads:
87        process = LiveProcess()
88        process.executable = wrkld
89        process.cwd = os.getcwd()
90
91        if len(pargs) > idx:
92            process.cmd = [wrkld] + pargs[idx].split()
93        else:
94            process.cmd = [wrkld]
95
96        if len(inputs) > idx:
97            process.input = inputs[idx]
98        if len(outputs) > idx:
99            process.output = outputs[idx]
100        if len(errouts) > idx:
101            process.errout = errouts[idx]
102
103        multiprocesses.append(process)
104        idx += 1
105
106    if options.smt:
107        assert(options.cpu_type == "detailed" or options.cpu_type == "inorder")
108        return multiprocesses, idx
109    else:
110        return multiprocesses, 1
111
112
113parser = optparse.OptionParser()
114Options.addCommonOptions(parser)
115Options.addSEOptions(parser)
116
117if '--ruby' in sys.argv:
118    Ruby.define_options(parser)
119
120(options, args) = parser.parse_args()
121
122if args:
123    print "Error: script doesn't take any positional arguments"
124    sys.exit(1)
125
126multiprocesses = []
127numThreads = 1
128
129if options.bench:
130    apps = options.bench.split("-")
131    if len(apps) != options.num_cpus:
132        print "number of benchmarks not equal to set num_cpus!"
133        sys.exit(1)
134
135    for app in apps:
136        try:
137            if buildEnv['TARGET_ISA'] == 'alpha':
138                exec("workload = %s('alpha', 'tru64', 'ref')" % app)
139            else:
140                exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
141            multiprocesses.append(workload.makeLiveProcess())
142        except:
143            print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
144            sys.exit(1)
145elif options.cmd:
146    multiprocesses, numThreads = get_processes(options)
147else:
148    print >> sys.stderr, "No workload specified. Exiting!\n"
149    sys.exit(1)
150
151
152(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
153CPUClass.numThreads = numThreads
154
155MemClass = Simulation.setMemClass(options)
156
157# Check -- do not allow SMT with multiple CPUs
158if options.smt and options.num_cpus > 1:
159    fatal("You cannot use SMT with multiple CPUs!")
160
161np = options.num_cpus
162system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
163                mem_mode = test_mem_mode,
164                mem_ranges = [AddrRange(options.mem_size)],
165                cache_line_size = options.cacheline_size)
166
167# Create a top-level voltage domain
168system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
169
170# Create a source clock for the system and set the clock period
171system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
172                                   voltage_domain = system.voltage_domain)
173
174# Create a CPU voltage domain
175system.cpu_voltage_domain = VoltageDomain()
176
177# Create a separate clock domain for the CPUs
178system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
179                                       voltage_domain =
180                                       system.cpu_voltage_domain)
181
182# All cpus belong to a common cpu_clk_domain, therefore running at a common
183# frequency.
184for cpu in system.cpu:
185    cpu.clk_domain = system.cpu_clk_domain
186
187# Sanity check
188if options.fastmem:
189    if CPUClass != AtomicSimpleCPU:
190        fatal("Fastmem can only be used with atomic CPU!")
191    if (options.caches or options.l2cache):
192        fatal("You cannot use fastmem in combination with caches!")
193
194if options.simpoint_profile:
195    if not options.fastmem:
196        # Atomic CPU checked with fastmem option already
197        fatal("SimPoint generation should be done with atomic cpu and fastmem")
198    if np > 1:
199        fatal("SimPoint generation not supported with more than one CPUs")
200
201for i in xrange(np):
202    if options.smt:
203        system.cpu[i].workload = multiprocesses
204    elif len(multiprocesses) == 1:
205        system.cpu[i].workload = multiprocesses[0]
206    else:
207        system.cpu[i].workload = multiprocesses[i]
208
209    if options.fastmem:
210        system.cpu[i].fastmem = True
211
212    if options.simpoint_profile:
213        system.cpu[i].simpoint_profile = True
214        system.cpu[i].simpoint_interval = options.simpoint_interval
215
216    if options.checker:
217        system.cpu[i].addCheckerCpu()
218
219    system.cpu[i].createThreads()
220
221if options.ruby:
222    if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
223        print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
224        sys.exit(1)
225
226    # Set the option for physmem so that it is not allocated any space
227    system.physmem = MemClass(range=AddrRange(options.mem_size),
228                              null = True)
229
230    options.use_map = True
231    Ruby.create_system(options, system)
232    assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
233
234    for i in xrange(np):
235        ruby_port = system.ruby._cpu_ruby_ports[i]
236
237        # Create the interrupt controller and connect its ports to Ruby
238        # Note that the interrupt controller is always present but only
239        # in x86 does it have message ports that need to be connected
240        system.cpu[i].createInterruptController()
241
242        # Connect the cpu's cache ports to Ruby
243        system.cpu[i].icache_port = ruby_port.slave
244        system.cpu[i].dcache_port = ruby_port.slave
245        if buildEnv['TARGET_ISA'] == 'x86':
246            system.cpu[i].interrupts.pio = ruby_port.master
247            system.cpu[i].interrupts.int_master = ruby_port.slave
248            system.cpu[i].interrupts.int_slave = ruby_port.master
249            system.cpu[i].itb.walker.port = ruby_port.slave
250            system.cpu[i].dtb.walker.port = ruby_port.slave
251else:
252    system.membus = CoherentBus()
253    system.system_port = system.membus.slave
254    CacheConfig.config_cache(options, system)
255    MemConfig.config_mem(options, system)
256
257root = Root(full_system = False, system = system)
258Simulation.run(options, root, system, FutureClass)
259