se.py revision 9836:4411b4e0c03a 
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
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17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
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25# this software without specific prior written permission.
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27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47
48import m5
49from m5.defines import buildEnv
50from m5.objects import *
51from m5.util import addToPath, fatal
52
53addToPath('../common')
54addToPath('../ruby')
55addToPath('../topologies')
56
57import Options
58import Ruby
59import Simulation
60import CacheConfig
61import MemConfig
62from Caches import *
63from cpu2000 import *
64
65def get_processes(options):
66    """Interprets provided options and returns a list of processes"""
67
68    multiprocesses = []
69    inputs = []
70    outputs = []
71    errouts = []
72    pargs = []
73
74    workloads = options.cmd.split(';')
75    if options.input != "":
76        inputs = options.input.split(';')
77    if options.output != "":
78        outputs = options.output.split(';')
79    if options.errout != "":
80        errouts = options.errout.split(';')
81    if options.options != "":
82        pargs = options.options.split(';')
83
84    idx = 0
85    for wrkld in workloads:
86        process = LiveProcess()
87        process.executable = wrkld
88
89        if len(pargs) > idx:
90            process.cmd = [wrkld] + pargs[idx].split()
91        else:
92            process.cmd = [wrkld]
93
94        if len(inputs) > idx:
95            process.input = inputs[idx]
96        if len(outputs) > idx:
97            process.output = outputs[idx]
98        if len(errouts) > idx:
99            process.errout = errouts[idx]
100
101        multiprocesses.append(process)
102        idx += 1
103
104    if options.smt:
105        assert(options.cpu_type == "detailed" or options.cpu_type == "inorder")
106        return multiprocesses, idx
107    else:
108        return multiprocesses, 1
109
110
111parser = optparse.OptionParser()
112Options.addCommonOptions(parser)
113Options.addSEOptions(parser)
114
115if '--ruby' in sys.argv:
116    Ruby.define_options(parser)
117
118(options, args) = parser.parse_args()
119
120if args:
121    print "Error: script doesn't take any positional arguments"
122    sys.exit(1)
123
124multiprocesses = []
125numThreads = 1
126
127if options.bench:
128    apps = options.bench.split("-")
129    if len(apps) != options.num_cpus:
130        print "number of benchmarks not equal to set num_cpus!"
131        sys.exit(1)
132
133    for app in apps:
134        try:
135            if buildEnv['TARGET_ISA'] == 'alpha':
136                exec("workload = %s('alpha', 'tru64', 'ref')" % app)
137            else:
138                exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
139            multiprocesses.append(workload.makeLiveProcess())
140        except:
141            print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
142            sys.exit(1)
143elif options.cmd:
144    multiprocesses, numThreads = get_processes(options)
145else:
146    print >> sys.stderr, "No workload specified. Exiting!\n"
147    sys.exit(1)
148
149
150(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
151CPUClass.numThreads = numThreads
152
153MemClass = Simulation.setMemClass(options)
154
155# Check -- do not allow SMT with multiple CPUs
156if options.smt and options.num_cpus > 1:
157    fatal("You cannot use SMT with multiple CPUs!")
158
159np = options.num_cpus
160system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
161                mem_mode = test_mem_mode,
162                mem_ranges = [AddrRange(options.mem_size)],
163                cache_line_size = options.cacheline_size)
164
165# Create a top-level voltage domain
166system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
167
168# Create a source clock for the system and set the clock period
169system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
170                                   voltage_domain = system.voltage_domain)
171
172# Create a CPU voltage domain
173system.cpu_voltage_domain = VoltageDomain()
174
175# Create a separate clock domain for the CPUs
176system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
177                                       voltage_domain =
178                                       system.cpu_voltage_domain)
179
180# All cpus belong to a common cpu_clk_domain, therefore running at a common
181# frequency.
182for cpu in system.cpu:
183    cpu.clk_domain = system.cpu_clk_domain
184
185# Sanity check
186if options.fastmem:
187    if CPUClass != AtomicSimpleCPU:
188        fatal("Fastmem can only be used with atomic CPU!")
189    if (options.caches or options.l2cache):
190        fatal("You cannot use fastmem in combination with caches!")
191
192if options.simpoint_profile:
193    if not options.fastmem:
194        # Atomic CPU checked with fastmem option already
195        fatal("SimPoint generation should be done with atomic cpu and fastmem")
196    if np > 1:
197        fatal("SimPoint generation not supported with more than one CPUs")
198
199for i in xrange(np):
200    if options.smt:
201        system.cpu[i].workload = multiprocesses
202    elif len(multiprocesses) == 1:
203        system.cpu[i].workload = multiprocesses[0]
204    else:
205        system.cpu[i].workload = multiprocesses[i]
206
207    if options.fastmem:
208        system.cpu[i].fastmem = True
209
210    if options.simpoint_profile:
211        system.cpu[i].simpoint_profile = True
212        system.cpu[i].simpoint_interval = options.simpoint_interval
213
214    if options.checker:
215        system.cpu[i].addCheckerCpu()
216
217    system.cpu[i].createThreads()
218
219if options.ruby:
220    if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
221        print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
222        sys.exit(1)
223
224    # Set the option for physmem so that it is not allocated any space
225    system.physmem = MemClass(range=AddrRange(options.mem_size),
226                              null = True)
227
228    options.use_map = True
229    Ruby.create_system(options, system)
230    assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
231
232    for i in xrange(np):
233        ruby_port = system.ruby._cpu_ruby_ports[i]
234
235        # Create the interrupt controller and connect its ports to Ruby
236        # Note that the interrupt controller is always present but only
237        # in x86 does it have message ports that need to be connected
238        system.cpu[i].createInterruptController()
239
240        # Connect the cpu's cache ports to Ruby
241        system.cpu[i].icache_port = ruby_port.slave
242        system.cpu[i].dcache_port = ruby_port.slave
243        if buildEnv['TARGET_ISA'] == 'x86':
244            system.cpu[i].interrupts.pio = ruby_port.master
245            system.cpu[i].interrupts.int_master = ruby_port.slave
246            system.cpu[i].interrupts.int_slave = ruby_port.master
247            system.cpu[i].itb.walker.port = ruby_port.slave
248            system.cpu[i].dtb.walker.port = ruby_port.slave
249else:
250    system.membus = CoherentBus()
251    system.system_port = system.membus.slave
252    CacheConfig.config_cache(options, system)
253    MemConfig.config_mem(options, system)
254
255root = Root(full_system = False, system = system)
256Simulation.run(options, root, system, FutureClass)
257