se.py revision 9815:3b3b94536547 
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
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25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47
48import m5
49from m5.defines import buildEnv
50from m5.objects import *
51from m5.util import addToPath, fatal
52
53addToPath('../common')
54addToPath('../ruby')
55addToPath('../topologies')
56
57import Options
58import Ruby
59import Simulation
60import CacheConfig
61from Caches import *
62from cpu2000 import *
63
64def get_processes(options):
65    """Interprets provided options and returns a list of processes"""
66
67    multiprocesses = []
68    inputs = []
69    outputs = []
70    errouts = []
71    pargs = []
72
73    workloads = options.cmd.split(';')
74    if options.input != "":
75        inputs = options.input.split(';')
76    if options.output != "":
77        outputs = options.output.split(';')
78    if options.errout != "":
79        errouts = options.errout.split(';')
80    if options.options != "":
81        pargs = options.options.split(';')
82
83    idx = 0
84    for wrkld in workloads:
85        process = LiveProcess()
86        process.executable = wrkld
87
88        if len(pargs) > idx:
89            process.cmd = [wrkld] + pargs[idx].split()
90        else:
91            process.cmd = [wrkld]
92
93        if len(inputs) > idx:
94            process.input = inputs[idx]
95        if len(outputs) > idx:
96            process.output = outputs[idx]
97        if len(errouts) > idx:
98            process.errout = errouts[idx]
99
100        multiprocesses.append(process)
101        idx += 1
102
103    if options.smt:
104        assert(options.cpu_type == "detailed" or options.cpu_type == "inorder")
105        return multiprocesses, idx
106    else:
107        return multiprocesses, 1
108
109
110parser = optparse.OptionParser()
111Options.addCommonOptions(parser)
112Options.addSEOptions(parser)
113
114if '--ruby' in sys.argv:
115    Ruby.define_options(parser)
116
117(options, args) = parser.parse_args()
118
119if args:
120    print "Error: script doesn't take any positional arguments"
121    sys.exit(1)
122
123multiprocesses = []
124numThreads = 1
125
126if options.bench:
127    apps = options.bench.split("-")
128    if len(apps) != options.num_cpus:
129        print "number of benchmarks not equal to set num_cpus!"
130        sys.exit(1)
131
132    for app in apps:
133        try:
134            if buildEnv['TARGET_ISA'] == 'alpha':
135                exec("workload = %s('alpha', 'tru64', 'ref')" % app)
136            else:
137                exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
138            multiprocesses.append(workload.makeLiveProcess())
139        except:
140            print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
141            sys.exit(1)
142elif options.cmd:
143    multiprocesses, numThreads = get_processes(options)
144else:
145    print >> sys.stderr, "No workload specified. Exiting!\n"
146    sys.exit(1)
147
148
149(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
150CPUClass.numThreads = numThreads
151
152MemClass = Simulation.setMemClass(options)
153
154# Check -- do not allow SMT with multiple CPUs
155if options.smt and options.num_cpus > 1:
156    fatal("You cannot use SMT with multiple CPUs!")
157
158np = options.num_cpus
159system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
160                physmem = MemClass(range=AddrRange(options.mem_size)),
161                mem_mode = test_mem_mode,
162                clk_domain = SrcClockDomain(clock = options.sys_clock),
163                cache_line_size = options.cacheline_size)
164
165# Create a separate clock domain for the CPUs
166system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
167
168# All cpus belong to a common cpu_clk_domain, therefore running at a common
169# frequency.
170for cpu in system.cpu:
171    cpu.clk_domain = system.cpu_clk_domain
172
173# Sanity check
174if options.fastmem:
175    if CPUClass != AtomicSimpleCPU:
176        fatal("Fastmem can only be used with atomic CPU!")
177    if (options.caches or options.l2cache):
178        fatal("You cannot use fastmem in combination with caches!")
179
180if options.simpoint_profile:
181    if not options.fastmem:
182        # Atomic CPU checked with fastmem option already
183        fatal("SimPoint generation should be done with atomic cpu and fastmem")
184    if np > 1:
185        fatal("SimPoint generation not supported with more than one CPUs")
186
187for i in xrange(np):
188    if options.smt:
189        system.cpu[i].workload = multiprocesses
190    elif len(multiprocesses) == 1:
191        system.cpu[i].workload = multiprocesses[0]
192    else:
193        system.cpu[i].workload = multiprocesses[i]
194
195    if options.fastmem:
196        system.cpu[i].fastmem = True
197
198    if options.simpoint_profile:
199        system.cpu[i].simpoint_profile = True
200        system.cpu[i].simpoint_interval = options.simpoint_interval
201
202    if options.checker:
203        system.cpu[i].addCheckerCpu()
204
205    system.cpu[i].createThreads()
206
207if options.ruby:
208    if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
209        print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
210        sys.exit(1)
211
212    # Set the option for physmem so that it is not allocated any space
213    system.physmem.null = True
214
215    options.use_map = True
216    Ruby.create_system(options, system)
217    assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
218
219    for i in xrange(np):
220        ruby_port = system.ruby._cpu_ruby_ports[i]
221
222        # Create the interrupt controller and connect its ports to Ruby
223        # Note that the interrupt controller is always present but only
224        # in x86 does it have message ports that need to be connected
225        system.cpu[i].createInterruptController()
226
227        # Connect the cpu's cache ports to Ruby
228        system.cpu[i].icache_port = ruby_port.slave
229        system.cpu[i].dcache_port = ruby_port.slave
230        if buildEnv['TARGET_ISA'] == 'x86':
231            system.cpu[i].interrupts.pio = ruby_port.master
232            system.cpu[i].interrupts.int_master = ruby_port.slave
233            system.cpu[i].interrupts.int_slave = ruby_port.master
234            system.cpu[i].itb.walker.port = ruby_port.slave
235            system.cpu[i].dtb.walker.port = ruby_port.slave
236else:
237    system.membus = CoherentBus()
238    system.system_port = system.membus.slave
239    system.physmem.port = system.membus.master
240    CacheConfig.config_cache(options, system)
241
242root = Root(full_system = False, system = system)
243Simulation.run(options, root, system, FutureClass)
244