se.py revision 6978:ab05e20dc4a7 
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29# Simple test script
30#
31# "m5 test.py"
32
33import os
34import optparse
35import sys
36from os.path import join as joinpath
37
38import m5
39from m5.defines import buildEnv
40from m5.objects import *
41from m5.util import addToPath, fatal
42
43if buildEnv['FULL_SYSTEM']:
44    fatal("This script requires syscall emulation mode (*_SE).")
45
46addToPath('../common')
47
48import Simulation
49from Caches import *
50from cpu2000 import *
51
52# Get paths we might need.  It's expected this file is in m5/configs/example.
53config_path = os.path.dirname(os.path.abspath(__file__))
54config_root = os.path.dirname(config_path)
55m5_root = os.path.dirname(config_root)
56
57parser = optparse.OptionParser()
58
59# Benchmark options
60parser.add_option("-c", "--cmd",
61    default=joinpath(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
62    help="The binary to run in syscall emulation mode.")
63parser.add_option("-o", "--options", default="",
64    help='The options to pass to the binary, use " " around the entire string')
65parser.add_option("-i", "--input", default="", help="Read stdin from a file.")
66parser.add_option("--output", default="", help="Redirect stdout to a file.")
67parser.add_option("--errout", default="", help="Redirect stderr to a file.")
68
69execfile(os.path.join(config_root, "common", "Options.py"))
70
71(options, args) = parser.parse_args()
72
73if args:
74    print "Error: script doesn't take any positional arguments"
75    sys.exit(1)
76
77if options.bench:
78    try:
79        if buildEnv['TARGET_ISA'] != 'alpha':
80            print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time"
81            sys.exit(1)
82        exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
83        process = workload.makeLiveProcess()
84    except:
85        print >>sys.stderr, "Unable to find workload for %s" % options.bench
86        sys.exit(1)
87else:
88    process = LiveProcess()
89    process.executable = options.cmd
90    process.cmd = [options.cmd] + options.options.split()
91
92
93if options.input != "":
94    process.input = options.input
95if options.output != "":
96    process.output = options.output
97if options.errout != "":
98    process.errout = options.errout
99
100
101# By default, set workload to path of user-specified binary
102workloads = options.cmd
103numThreads = 1
104
105if options.detailed or options.inorder:
106    #check for SMT workload
107    workloads = options.cmd.split(';')
108    if len(workloads) > 1:
109        process = []
110        smt_idx = 0
111        inputs = []
112        outputs = []
113        errouts = []
114
115        if options.input != "":
116            inputs = options.input.split(';')
117        if options.output != "":
118            outputs = options.output.split(';')
119        if options.errout != "":
120            errouts = options.errout.split(';')
121
122        for wrkld in workloads:
123            smt_process = LiveProcess()
124            smt_process.executable = wrkld
125            smt_process.cmd = wrkld + " " + options.options
126            if inputs and inputs[smt_idx]:
127                smt_process.input = inputs[smt_idx]
128            if outputs and outputs[smt_idx]:
129                smt_process.output = outputs[smt_idx]
130            if errouts and errouts[smt_idx]:
131                smt_process.errout = errouts[smt_idx]
132            process += [smt_process, ]
133            smt_idx += 1
134    numThreads = len(workloads)
135
136(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
137
138CPUClass.clock = '2GHz'
139CPUClass.numThreads = numThreads;
140
141np = options.num_cpus
142
143system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
144                physmem = PhysicalMemory(range=AddrRange("512MB")),
145                membus = Bus(), mem_mode = test_mem_mode)
146
147system.physmem.port = system.membus.port
148
149if options.l2cache:
150    system.l2 = L2Cache(size='2MB')
151    system.tol2bus = Bus()
152    system.l2.cpu_side = system.tol2bus.port
153    system.l2.mem_side = system.membus.port
154    system.l2.num_cpus = np
155
156for i in xrange(np):
157    if options.caches:
158        system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
159                                              L1Cache(size = '64kB'))
160    if options.l2cache:
161        system.cpu[i].connectMemPorts(system.tol2bus)
162    else:
163        system.cpu[i].connectMemPorts(system.membus)
164    system.cpu[i].workload = process
165
166    if options.fastmem:
167        system.cpu[0].physmem_port = system.physmem.port
168
169root = Root(system = system)
170
171Simulation.run(options, root, system, FutureClass)
172