se.py revision 4968:f1c856d8c460 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29# Simple test script
30#
31# "m5 test.py"
32
33import m5
34from m5.objects import *
35import os, optparse, sys
36m5.AddToPath('../common')
37import Simulation
38from Caches import *
39
40# Get paths we might need.  It's expected this file is in m5/configs/example.
41config_path = os.path.dirname(os.path.abspath(__file__))
42config_root = os.path.dirname(config_path)
43m5_root = os.path.dirname(config_root)
44
45parser = optparse.OptionParser()
46
47# Benchmark options
48parser.add_option("-c", "--cmd",
49                  default=os.path.join(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
50                  help="The binary to run in syscall emulation mode.")
51parser.add_option("-o", "--options", default="",
52                  help="The options to pass to the binary, use \" \" around the entire\
53                        string.")
54parser.add_option("-i", "--input", default="",
55                  help="A file of input to give to the binary.")
56
57execfile(os.path.join(config_root, "common", "Options.py"))
58
59(options, args) = parser.parse_args()
60
61if args:
62    print "Error: script doesn't take any positional arguments"
63    sys.exit(1)
64
65process = LiveProcess()
66process.executable = options.cmd
67process.cmd = [options.cmd] + options.options.split()
68if options.input != "":
69    process.input = options.input
70
71if options.detailed:
72    #check for SMT workload
73    workloads = options.cmd.split(';')
74    if len(workloads) > 1:
75        process = []
76        smt_idx = 0
77        inputs = []
78
79        if options.input != "":
80            inputs = options.input.split(';')
81
82        for wrkld in workloads:
83            smt_process = LiveProcess()
84            smt_process.executable = wrkld
85            smt_process.cmd = wrkld + " " + options.options
86            if inputs and inputs[smt_idx]:
87                smt_process.input = inputs[smt_idx]
88            process += [smt_process, ]
89            smt_idx += 1
90
91(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
92
93CPUClass.clock = '2GHz'
94
95np = options.num_cpus
96
97system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
98                physmem = PhysicalMemory(range=AddrRange("512MB")),
99                membus = Bus(), mem_mode = test_mem_mode)
100
101system.physmem.port = system.membus.port
102
103for i in xrange(np):
104    if options.caches:
105        system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
106                                              L1Cache(size = '64kB'))
107    if options.l2cache:
108        system.l2 = L2Cache(size='2MB')
109        system.tol2bus = Bus()
110        system.l2.cpu_side = system.tol2bus.port
111        system.l2.mem_side = system.membus.port
112        system.cpu[i].connectMemPorts(system.tol2bus)
113    else:
114        system.cpu[i].connectMemPorts(system.membus)
115    system.cpu[i].workload = process
116
117    if options.fastmem:
118        system.cpu[0].physmem_port = system.physmem.port
119
120root = Root(system = system)
121
122Simulation.run(options, root, system, FutureClass)
123