se.py revision 3395:49e674f2fb5d
18981Sandreas.hansson@arm.com# Copyright (c) 2006 The Regents of The University of Michigan 28981Sandreas.hansson@arm.com# All rights reserved. 38981Sandreas.hansson@arm.com# 48981Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 58981Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 68981Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 78981Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 88981Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 98981Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 108981Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 118981Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 128981Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 138981Sandreas.hansson@arm.com# this software without specific prior written permission. 148981Sandreas.hansson@arm.com# 158981Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 168981Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 178981Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 188981Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 198981Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 208981Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 218981Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 228981Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 238981Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 248981Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 258981Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 268981Sandreas.hansson@arm.com# 278981Sandreas.hansson@arm.com# Authors: Steve Reinhardt 288981Sandreas.hansson@arm.com 298981Sandreas.hansson@arm.com# Simple test script 308981Sandreas.hansson@arm.com# 318981Sandreas.hansson@arm.com# "m5 test.py" 328981Sandreas.hansson@arm.com 338981Sandreas.hansson@arm.comimport m5 348981Sandreas.hansson@arm.comfrom m5.objects import * 358981Sandreas.hansson@arm.comimport os, optparse, sys 368981Sandreas.hansson@arm.comm5.AddToPath('../common') 378981Sandreas.hansson@arm.comimport Simulation 388981Sandreas.hansson@arm.com 398981Sandreas.hansson@arm.comparser = optparse.OptionParser() 408981Sandreas.hansson@arm.com 418981Sandreas.hansson@arm.com# Benchmark options 428981Sandreas.hansson@arm.comparser.add_option("-c", "--cmd", 438981Sandreas.hansson@arm.com default="../../tests/test-progs/hello/bin/alpha/linux/hello", 448981Sandreas.hansson@arm.com help="The binary to run in syscall emulation mode.") 458981Sandreas.hansson@arm.comparser.add_option("-o", "--options", default="", 468981Sandreas.hansson@arm.com help="The options to pass to the binary, use \" \" around the entire\ 478981Sandreas.hansson@arm.com string.") 488981Sandreas.hansson@arm.comparser.add_option("-i", "--input", default="", 498981Sandreas.hansson@arm.com help="A file of input to give to the binary.") 508981Sandreas.hansson@arm.com 518981Sandreas.hansson@arm.comexecfile("Options.py") 528981Sandreas.hansson@arm.com 538981Sandreas.hansson@arm.com(options, args) = parser.parse_args() 548981Sandreas.hansson@arm.com 558981Sandreas.hansson@arm.comif args: 568981Sandreas.hansson@arm.com print "Error: script doesn't take any positional arguments" 578981Sandreas.hansson@arm.com sys.exit(1) 588981Sandreas.hansson@arm.com 598981Sandreas.hansson@arm.comprocess = LiveProcess() 608981Sandreas.hansson@arm.comprocess.executable = options.cmd 618981Sandreas.hansson@arm.comprocess.cmd = options.cmd + " " + options.options 628981Sandreas.hansson@arm.comif options.input != "": 638981Sandreas.hansson@arm.com process.input = options.input 648981Sandreas.hansson@arm.com 658981Sandreas.hansson@arm.comif options.detailed: 668981Sandreas.hansson@arm.com #check for SMT workload 678981Sandreas.hansson@arm.com workloads = options.cmd.split(';') 688981Sandreas.hansson@arm.com if len(workloads) > 1: 698981Sandreas.hansson@arm.com process = [] 708981Sandreas.hansson@arm.com smt_idx = 0 718981Sandreas.hansson@arm.com inputs = [] 728981Sandreas.hansson@arm.com 738981Sandreas.hansson@arm.com if options.input != "": 748981Sandreas.hansson@arm.com inputs = options.input.split(';') 758981Sandreas.hansson@arm.com 768981Sandreas.hansson@arm.com for wrkld in workloads: 778981Sandreas.hansson@arm.com smt_process = LiveProcess() 788981Sandreas.hansson@arm.com smt_process.executable = wrkld 798981Sandreas.hansson@arm.com smt_process.cmd = wrkld + " " + options.options 808981Sandreas.hansson@arm.com if inputs and inputs[smt_idx]: 818981Sandreas.hansson@arm.com smt_process.input = inputs[smt_idx] 828981Sandreas.hansson@arm.com process += [smt_process, ] 838981Sandreas.hansson@arm.com smt_idx += 1 848981Sandreas.hansson@arm.com 858981Sandreas.hansson@arm.com 868981Sandreas.hansson@arm.comif options.timing: 878981Sandreas.hansson@arm.com CPUClass = TimingSimpleCPU 888981Sandreas.hansson@arm.com test_mem_mode = 'timing' 898981Sandreas.hansson@arm.comelif options.detailed: 908981Sandreas.hansson@arm.com CPUClass = DerivO3CPU 918981Sandreas.hansson@arm.com test_mem_mode = 'timing' 928981Sandreas.hansson@arm.comelse: 938981Sandreas.hansson@arm.com CPUClass = AtomicSimpleCPU 948981Sandreas.hansson@arm.com test_mem_mode = 'atomic' 958981Sandreas.hansson@arm.com 968981Sandreas.hansson@arm.comCPUClass.clock = '2GHz' 978981Sandreas.hansson@arm.com 988981Sandreas.hansson@arm.comnp = options.num_cpus 998981Sandreas.hansson@arm.com 1008981Sandreas.hansson@arm.comsystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 1018981Sandreas.hansson@arm.com physmem = PhysicalMemory(range=AddrRange("512MB")), 1028981Sandreas.hansson@arm.com membus = Bus(), mem_mode = test_mem_mode) 1038981Sandreas.hansson@arm.com 1048981Sandreas.hansson@arm.comsystem.physmem.port = system.membus.port 1058981Sandreas.hansson@arm.com 1068981Sandreas.hansson@arm.comfor i in xrange(np): 1078981Sandreas.hansson@arm.com if options.caches and not options.standard_switch: 1088981Sandreas.hansson@arm.com system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 1098981Sandreas.hansson@arm.com L2Cache(size = '64kB')) 1108981Sandreas.hansson@arm.com system.cpu[i].connectMemPorts(system.membus) 1118981Sandreas.hansson@arm.com system.cpu[i].mem = system.physmem 1128981Sandreas.hansson@arm.com system.cpu[i].workload = process 1138981Sandreas.hansson@arm.com 1148981Sandreas.hansson@arm.comroot = Root(system = system) 1158981Sandreas.hansson@arm.com 1168981Sandreas.hansson@arm.comSimulation.run(options, root, system) 1178981Sandreas.hansson@arm.com