se.py revision 13774
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2008 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Steve Reinhardt 40 41# Simple test script 42# 43# "m5 test.py" 44 45from __future__ import print_function 46from __future__ import absolute_import 47 48import optparse 49import sys 50import os 51 52import m5 53from m5.defines import buildEnv 54from m5.objects import * 55from m5.util import addToPath, fatal, warn 56 57addToPath('../') 58 59from ruby import Ruby 60 61from common import Options 62from common import Simulation 63from common import CacheConfig 64from common import CpuConfig 65from common import BPConfig 66from common import MemConfig 67from common.Caches import * 68from common.cpu2000 import * 69 70def get_processes(options): 71 """Interprets provided options and returns a list of processes""" 72 73 multiprocesses = [] 74 inputs = [] 75 outputs = [] 76 errouts = [] 77 pargs = [] 78 79 workloads = options.cmd.split(';') 80 if options.input != "": 81 inputs = options.input.split(';') 82 if options.output != "": 83 outputs = options.output.split(';') 84 if options.errout != "": 85 errouts = options.errout.split(';') 86 if options.options != "": 87 pargs = options.options.split(';') 88 89 idx = 0 90 for wrkld in workloads: 91 process = Process(pid = 100 + idx) 92 process.executable = wrkld 93 process.cwd = os.getcwd() 94 95 if options.env: 96 with open(options.env, 'r') as f: 97 process.env = [line.rstrip() for line in f] 98 99 if len(pargs) > idx: 100 process.cmd = [wrkld] + pargs[idx].split() 101 else: 102 process.cmd = [wrkld] 103 104 if len(inputs) > idx: 105 process.input = inputs[idx] 106 if len(outputs) > idx: 107 process.output = outputs[idx] 108 if len(errouts) > idx: 109 process.errout = errouts[idx] 110 111 multiprocesses.append(process) 112 idx += 1 113 114 if options.smt: 115 assert(options.cpu_type == "DerivO3CPU") 116 return multiprocesses, idx 117 else: 118 return multiprocesses, 1 119 120 121parser = optparse.OptionParser() 122Options.addCommonOptions(parser) 123Options.addSEOptions(parser) 124 125if '--ruby' in sys.argv: 126 Ruby.define_options(parser) 127 128(options, args) = parser.parse_args() 129 130if args: 131 print("Error: script doesn't take any positional arguments") 132 sys.exit(1) 133 134multiprocesses = [] 135numThreads = 1 136 137if options.bench: 138 apps = options.bench.split("-") 139 if len(apps) != options.num_cpus: 140 print("number of benchmarks not equal to set num_cpus!") 141 sys.exit(1) 142 143 for app in apps: 144 try: 145 if buildEnv['TARGET_ISA'] == 'alpha': 146 exec("workload = %s('alpha', 'tru64', '%s')" % ( 147 app, options.spec_input)) 148 elif buildEnv['TARGET_ISA'] == 'arm': 149 exec("workload = %s('arm_%s', 'linux', '%s')" % ( 150 app, options.arm_iset, options.spec_input)) 151 else: 152 exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % ( 153 app, options.spec_input)) 154 multiprocesses.append(workload.makeProcess()) 155 except: 156 print("Unable to find workload for %s: %s" % 157 (buildEnv['TARGET_ISA'], app), 158 file=sys.stderr) 159 sys.exit(1) 160elif options.cmd: 161 multiprocesses, numThreads = get_processes(options) 162else: 163 print("No workload specified. Exiting!\n", file=sys.stderr) 164 sys.exit(1) 165 166 167(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 168CPUClass.numThreads = numThreads 169 170# Check -- do not allow SMT with multiple CPUs 171if options.smt and options.num_cpus > 1: 172 fatal("You cannot use SMT with multiple CPUs!") 173 174np = options.num_cpus 175system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)], 176 mem_mode = test_mem_mode, 177 mem_ranges = [AddrRange(options.mem_size)], 178 cache_line_size = options.cacheline_size) 179 180if numThreads > 1: 181 system.multi_thread = True 182 183# Create a top-level voltage domain 184system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 185 186# Create a source clock for the system and set the clock period 187system.clk_domain = SrcClockDomain(clock = options.sys_clock, 188 voltage_domain = system.voltage_domain) 189 190# Create a CPU voltage domain 191system.cpu_voltage_domain = VoltageDomain() 192 193# Create a separate clock domain for the CPUs 194system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 195 voltage_domain = 196 system.cpu_voltage_domain) 197 198# If elastic tracing is enabled, then configure the cpu and attach the elastic 199# trace probe 200if options.elastic_trace_en: 201 CpuConfig.config_etrace(CPUClass, system.cpu, options) 202 203# All cpus belong to a common cpu_clk_domain, therefore running at a common 204# frequency. 205for cpu in system.cpu: 206 cpu.clk_domain = system.cpu_clk_domain 207 208if CpuConfig.is_kvm_cpu(CPUClass) or CpuConfig.is_kvm_cpu(FutureClass): 209 if buildEnv['TARGET_ISA'] == 'x86': 210 system.kvm_vm = KvmVM() 211 for process in multiprocesses: 212 process.useArchPT = True 213 process.kvmInSE = True 214 else: 215 fatal("KvmCPU can only be used in SE mode with x86") 216 217# Sanity check 218if options.simpoint_profile: 219 if not CpuConfig.is_noncaching_cpu(CPUClass): 220 fatal("SimPoint/BPProbe should be done with an atomic cpu") 221 if np > 1: 222 fatal("SimPoint generation not supported with more than one CPUs") 223 224for i in range(np): 225 if options.smt: 226 system.cpu[i].workload = multiprocesses 227 elif len(multiprocesses) == 1: 228 system.cpu[i].workload = multiprocesses[0] 229 else: 230 system.cpu[i].workload = multiprocesses[i] 231 232 if options.simpoint_profile: 233 system.cpu[i].addSimPointProbe(options.simpoint_interval) 234 235 if options.checker: 236 system.cpu[i].addCheckerCpu() 237 238 if options.bp_type: 239 bpClass = BPConfig.get(options.bp_type) 240 system.cpu[i].branchPred = bpClass() 241 242 system.cpu[i].createThreads() 243 244if options.ruby: 245 Ruby.create_system(options, False, system) 246 assert(options.num_cpus == len(system.ruby._cpu_ports)) 247 248 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 249 voltage_domain = system.voltage_domain) 250 for i in range(np): 251 ruby_port = system.ruby._cpu_ports[i] 252 253 # Create the interrupt controller and connect its ports to Ruby 254 # Note that the interrupt controller is always present but only 255 # in x86 does it have message ports that need to be connected 256 system.cpu[i].createInterruptController() 257 258 # Connect the cpu's cache ports to Ruby 259 system.cpu[i].icache_port = ruby_port.slave 260 system.cpu[i].dcache_port = ruby_port.slave 261 if buildEnv['TARGET_ISA'] == 'x86': 262 system.cpu[i].interrupts[0].pio = ruby_port.master 263 system.cpu[i].interrupts[0].int_master = ruby_port.slave 264 system.cpu[i].interrupts[0].int_slave = ruby_port.master 265 system.cpu[i].itb.walker.port = ruby_port.slave 266 system.cpu[i].dtb.walker.port = ruby_port.slave 267else: 268 MemClass = Simulation.setMemClass(options) 269 system.membus = SystemXBar() 270 system.system_port = system.membus.slave 271 CacheConfig.config_cache(options, system) 272 MemConfig.config_mem(options, system) 273 274root = Root(full_system = False, system = system) 275Simulation.run(options, root, system, FutureClass) 276