se.py revision 11839:dd6df2e47c14
110066Sandreas.hansson@arm.com# Copyright (c) 2012-2013 ARM Limited 210066Sandreas.hansson@arm.com# All rights reserved. 310066Sandreas.hansson@arm.com# 410066Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 510066Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 610066Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 710066Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 810066Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 910066Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 1010066Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 1110066Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 1210066Sandreas.hansson@arm.com# 1310066Sandreas.hansson@arm.com# Copyright (c) 2006-2008 The Regents of The University of Michigan 1410066Sandreas.hansson@arm.com# All rights reserved. 1510066Sandreas.hansson@arm.com# 1610066Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 1710066Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 1810066Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 1910066Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 2010066Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 2110066Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 2210066Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 2310066Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 2410066Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 2510066Sandreas.hansson@arm.com# this software without specific prior written permission. 2610066Sandreas.hansson@arm.com# 2710066Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2810066Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2910066Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3010066Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3110066Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3210066Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3310066Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3410066Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3510066Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3610066Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3710066Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3810066Sandreas.hansson@arm.com# 3910066Sandreas.hansson@arm.com# Authors: Steve Reinhardt 4010066Sandreas.hansson@arm.com 4110066Sandreas.hansson@arm.com# Simple test script 4210066Sandreas.hansson@arm.com# 4310066Sandreas.hansson@arm.com# "m5 test.py" 4410066Sandreas.hansson@arm.com 4510066Sandreas.hansson@arm.comimport optparse 4610066Sandreas.hansson@arm.comimport sys 4710066Sandreas.hansson@arm.comimport os 4810066Sandreas.hansson@arm.com 4910066Sandreas.hansson@arm.comimport m5 5010066Sandreas.hansson@arm.comfrom m5.defines import buildEnv 5110066Sandreas.hansson@arm.comfrom m5.objects import * 5210066Sandreas.hansson@arm.comfrom m5.util import addToPath, fatal 5310296Sandreas.hansson@arm.com 5410066Sandreas.hansson@arm.comaddToPath('../') 5510066Sandreas.hansson@arm.com 5610066Sandreas.hansson@arm.comfrom ruby import Ruby 5710066Sandreas.hansson@arm.com 5810066Sandreas.hansson@arm.comfrom common import Options 5910066Sandreas.hansson@arm.comfrom common import Simulation 6010066Sandreas.hansson@arm.comfrom common import CacheConfig 6110066Sandreas.hansson@arm.comfrom common import CpuConfig 6210066Sandreas.hansson@arm.comfrom common import MemConfig 6310066Sandreas.hansson@arm.comfrom common.Caches import * 6410066Sandreas.hansson@arm.comfrom common.cpu2000 import * 6510066Sandreas.hansson@arm.com 6610066Sandreas.hansson@arm.com# Check if KVM support has been enabled, we might need to do VM 6710066Sandreas.hansson@arm.com# configuration if that's the case. 6810066Sandreas.hansson@arm.comhave_kvm_support = 'BaseKvmCPU' in globals() 6910066Sandreas.hansson@arm.comdef is_kvm_cpu(cpu_class): 7010066Sandreas.hansson@arm.com return have_kvm_support and cpu_class != None and \ 7110066Sandreas.hansson@arm.com issubclass(cpu_class, BaseKvmCPU) 7210066Sandreas.hansson@arm.com 7310066Sandreas.hansson@arm.comdef get_processes(options): 7410066Sandreas.hansson@arm.com """Interprets provided options and returns a list of processes""" 7510066Sandreas.hansson@arm.com 7610066Sandreas.hansson@arm.com multiprocesses = [] 7710066Sandreas.hansson@arm.com inputs = [] 7810066Sandreas.hansson@arm.com outputs = [] 7910066Sandreas.hansson@arm.com errouts = [] 8010466Sandreas.hansson@arm.com pargs = [] 8110466Sandreas.hansson@arm.com 8210066Sandreas.hansson@arm.com workloads = options.cmd.split(';') 8310066Sandreas.hansson@arm.com if options.input != "": 8410066Sandreas.hansson@arm.com inputs = options.input.split(';') 8510066Sandreas.hansson@arm.com if options.output != "": 8610066Sandreas.hansson@arm.com outputs = options.output.split(';') 8710066Sandreas.hansson@arm.com if options.errout != "": 8810066Sandreas.hansson@arm.com errouts = options.errout.split(';') 8910066Sandreas.hansson@arm.com if options.options != "": 9010066Sandreas.hansson@arm.com pargs = options.options.split(';') 9110066Sandreas.hansson@arm.com 9210066Sandreas.hansson@arm.com idx = 0 9310066Sandreas.hansson@arm.com for wrkld in workloads: 9410066Sandreas.hansson@arm.com process = LiveProcess() 9510066Sandreas.hansson@arm.com process.executable = wrkld 9610296Sandreas.hansson@arm.com process.cwd = os.getcwd() 9710296Sandreas.hansson@arm.com 9810066Sandreas.hansson@arm.com if options.env: 9910066Sandreas.hansson@arm.com with open(options.env, 'r') as f: 10010066Sandreas.hansson@arm.com process.env = [line.rstrip() for line in f] 10110066Sandreas.hansson@arm.com 10210066Sandreas.hansson@arm.com if len(pargs) > idx: 10310066Sandreas.hansson@arm.com process.cmd = [wrkld] + pargs[idx].split() 10410066Sandreas.hansson@arm.com else: 10510066Sandreas.hansson@arm.com process.cmd = [wrkld] 10610066Sandreas.hansson@arm.com 10710066Sandreas.hansson@arm.com if len(inputs) > idx: 10810066Sandreas.hansson@arm.com process.input = inputs[idx] 10910066Sandreas.hansson@arm.com if len(outputs) > idx: 11010066Sandreas.hansson@arm.com process.output = outputs[idx] 11110066Sandreas.hansson@arm.com if len(errouts) > idx: 11210066Sandreas.hansson@arm.com process.errout = errouts[idx] 11310066Sandreas.hansson@arm.com 11410066Sandreas.hansson@arm.com multiprocesses.append(process) 11510066Sandreas.hansson@arm.com idx += 1 11610066Sandreas.hansson@arm.com 11710066Sandreas.hansson@arm.com if options.smt: 11810066Sandreas.hansson@arm.com assert(options.cpu_type == "detailed") 11910066Sandreas.hansson@arm.com return multiprocesses, idx 12010066Sandreas.hansson@arm.com else: 12110066Sandreas.hansson@arm.com return multiprocesses, 1 12210066Sandreas.hansson@arm.com 12310066Sandreas.hansson@arm.com 12410066Sandreas.hansson@arm.comparser = optparse.OptionParser() 12510066Sandreas.hansson@arm.comOptions.addCommonOptions(parser) 12610066Sandreas.hansson@arm.comOptions.addSEOptions(parser) 12710066Sandreas.hansson@arm.com 12810066Sandreas.hansson@arm.comif '--ruby' in sys.argv: 12910066Sandreas.hansson@arm.com Ruby.define_options(parser) 13010066Sandreas.hansson@arm.com 13110066Sandreas.hansson@arm.com(options, args) = parser.parse_args() 13210066Sandreas.hansson@arm.com 13310066Sandreas.hansson@arm.comif args: 13410066Sandreas.hansson@arm.com print "Error: script doesn't take any positional arguments" 13510066Sandreas.hansson@arm.com sys.exit(1) 13610066Sandreas.hansson@arm.com 13710066Sandreas.hansson@arm.commultiprocesses = [] 13810066Sandreas.hansson@arm.comnumThreads = 1 13910066Sandreas.hansson@arm.com 14010066Sandreas.hansson@arm.comif options.bench: 14110066Sandreas.hansson@arm.com apps = options.bench.split("-") 14210066Sandreas.hansson@arm.com if len(apps) != options.num_cpus: 14310066Sandreas.hansson@arm.com print "number of benchmarks not equal to set num_cpus!" 14410066Sandreas.hansson@arm.com sys.exit(1) 14510066Sandreas.hansson@arm.com 14610066Sandreas.hansson@arm.com for app in apps: 14710066Sandreas.hansson@arm.com try: 14810066Sandreas.hansson@arm.com if buildEnv['TARGET_ISA'] == 'alpha': 14910066Sandreas.hansson@arm.com exec("workload = %s('alpha', 'tru64', '%s')" % ( 15010066Sandreas.hansson@arm.com app, options.spec_input)) 15110066Sandreas.hansson@arm.com elif buildEnv['TARGET_ISA'] == 'arm': 15210066Sandreas.hansson@arm.com exec("workload = %s('arm_%s', 'linux', '%s')" % ( 15310066Sandreas.hansson@arm.com app, options.arm_iset, options.spec_input)) 15410066Sandreas.hansson@arm.com else: 15510066Sandreas.hansson@arm.com exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % ( 15610066Sandreas.hansson@arm.com app, options.spec_input)) 15710066Sandreas.hansson@arm.com multiprocesses.append(workload.makeLiveProcess()) 15810066Sandreas.hansson@arm.com except: 15910066Sandreas.hansson@arm.com print >>sys.stderr, "Unable to find workload for %s: %s" % ( 16010066Sandreas.hansson@arm.com buildEnv['TARGET_ISA'], app) 16110066Sandreas.hansson@arm.com sys.exit(1) 16210066Sandreas.hansson@arm.comelif options.cmd: 16310066Sandreas.hansson@arm.com multiprocesses, numThreads = get_processes(options) 16410066Sandreas.hansson@arm.comelse: 16510066Sandreas.hansson@arm.com print >> sys.stderr, "No workload specified. Exiting!\n" 16610066Sandreas.hansson@arm.com sys.exit(1) 16710066Sandreas.hansson@arm.com 16810066Sandreas.hansson@arm.com 16910066Sandreas.hansson@arm.com(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 17010066Sandreas.hansson@arm.comCPUClass.numThreads = numThreads 17110066Sandreas.hansson@arm.com 17210066Sandreas.hansson@arm.com# Check -- do not allow SMT with multiple CPUs 17310066Sandreas.hansson@arm.comif options.smt and options.num_cpus > 1: 17410066Sandreas.hansson@arm.com fatal("You cannot use SMT with multiple CPUs!") 17510066Sandreas.hansson@arm.com 17610066Sandreas.hansson@arm.comnp = options.num_cpus 17710066Sandreas.hansson@arm.comsystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 17810066Sandreas.hansson@arm.com mem_mode = test_mem_mode, 17910066Sandreas.hansson@arm.com mem_ranges = [AddrRange(options.mem_size)], 18010066Sandreas.hansson@arm.com cache_line_size = options.cacheline_size) 18110066Sandreas.hansson@arm.com 18210066Sandreas.hansson@arm.comif numThreads > 1: 18310066Sandreas.hansson@arm.com system.multi_thread = True 18410066Sandreas.hansson@arm.com 18510066Sandreas.hansson@arm.com# Create a top-level voltage domain 18610066Sandreas.hansson@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 18710066Sandreas.hansson@arm.com 18810066Sandreas.hansson@arm.com# Create a source clock for the system and set the clock period 18910066Sandreas.hansson@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 19010066Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 19110066Sandreas.hansson@arm.com 19210066Sandreas.hansson@arm.com# Create a CPU voltage domain 19310066Sandreas.hansson@arm.comsystem.cpu_voltage_domain = VoltageDomain() 19410066Sandreas.hansson@arm.com 19510066Sandreas.hansson@arm.com# Create a separate clock domain for the CPUs 19610066Sandreas.hansson@arm.comsystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 19710066Sandreas.hansson@arm.com voltage_domain = 19810066Sandreas.hansson@arm.com system.cpu_voltage_domain) 19910066Sandreas.hansson@arm.com 20010066Sandreas.hansson@arm.com# If elastic tracing is enabled, then configure the cpu and attach the elastic 20110066Sandreas.hansson@arm.com# trace probe 20210066Sandreas.hansson@arm.comif options.elastic_trace_en: 20310066Sandreas.hansson@arm.com CpuConfig.config_etrace(CPUClass, system.cpu, options) 20410066Sandreas.hansson@arm.com 20510066Sandreas.hansson@arm.com# All cpus belong to a common cpu_clk_domain, therefore running at a common 20610066Sandreas.hansson@arm.com# frequency. 20710066Sandreas.hansson@arm.comfor cpu in system.cpu: 20810066Sandreas.hansson@arm.com cpu.clk_domain = system.cpu_clk_domain 20910066Sandreas.hansson@arm.com 21010066Sandreas.hansson@arm.comif is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass): 21110066Sandreas.hansson@arm.com if buildEnv['TARGET_ISA'] == 'x86': 21210066Sandreas.hansson@arm.com system.kvm_vm = KvmVM() 21310066Sandreas.hansson@arm.com for process in multiprocesses: 21410066Sandreas.hansson@arm.com process.useArchPT = True 21510066Sandreas.hansson@arm.com process.kvmInSE = True 21610066Sandreas.hansson@arm.com else: 21710066Sandreas.hansson@arm.com fatal("KvmCPU can only be used in SE mode with x86") 21810066Sandreas.hansson@arm.com 21910066Sandreas.hansson@arm.com# Sanity check 22010066Sandreas.hansson@arm.comif options.fastmem: 22110066Sandreas.hansson@arm.com if CPUClass != AtomicSimpleCPU: 22210066Sandreas.hansson@arm.com fatal("Fastmem can only be used with atomic CPU!") 22310066Sandreas.hansson@arm.com if (options.caches or options.l2cache): 22410066Sandreas.hansson@arm.com fatal("You cannot use fastmem in combination with caches!") 22510066Sandreas.hansson@arm.com 22610066Sandreas.hansson@arm.comif options.simpoint_profile: 22710066Sandreas.hansson@arm.com if not options.fastmem: 22810066Sandreas.hansson@arm.com # Atomic CPU checked with fastmem option already 22910066Sandreas.hansson@arm.com fatal("SimPoint generation should be done with atomic cpu and fastmem") 23010066Sandreas.hansson@arm.com if np > 1: 23110066Sandreas.hansson@arm.com fatal("SimPoint generation not supported with more than one CPUs") 23210066Sandreas.hansson@arm.com 23310066Sandreas.hansson@arm.comfor i in xrange(np): 23410066Sandreas.hansson@arm.com if options.smt: 23510066Sandreas.hansson@arm.com system.cpu[i].workload = multiprocesses 23610066Sandreas.hansson@arm.com elif len(multiprocesses) == 1: 23710066Sandreas.hansson@arm.com system.cpu[i].workload = multiprocesses[0] 23810066Sandreas.hansson@arm.com else: 23910066Sandreas.hansson@arm.com system.cpu[i].workload = multiprocesses[i] 24010066Sandreas.hansson@arm.com 24110066Sandreas.hansson@arm.com if options.fastmem: 24210066Sandreas.hansson@arm.com system.cpu[i].fastmem = True 24310066Sandreas.hansson@arm.com 24410066Sandreas.hansson@arm.com if options.simpoint_profile: 24510066Sandreas.hansson@arm.com system.cpu[i].addSimPointProbe(options.simpoint_interval) 24610066Sandreas.hansson@arm.com 24710066Sandreas.hansson@arm.com if options.checker: 24810066Sandreas.hansson@arm.com system.cpu[i].addCheckerCpu() 24910066Sandreas.hansson@arm.com 25010066Sandreas.hansson@arm.com system.cpu[i].createThreads() 25110066Sandreas.hansson@arm.com 25210066Sandreas.hansson@arm.comif options.ruby: 25310066Sandreas.hansson@arm.com if options.cpu_type == "atomic" or options.cpu_type == "AtomicSimpleCPU": 25410066Sandreas.hansson@arm.com print >> sys.stderr, "Ruby does not work with atomic cpu!!" 25510066Sandreas.hansson@arm.com sys.exit(1) 25610066Sandreas.hansson@arm.com 25710066Sandreas.hansson@arm.com Ruby.create_system(options, False, system) 25810066Sandreas.hansson@arm.com assert(options.num_cpus == len(system.ruby._cpu_ports)) 25910066Sandreas.hansson@arm.com 26010066Sandreas.hansson@arm.com system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 26110066Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 26210066Sandreas.hansson@arm.com for i in xrange(np): 26310066Sandreas.hansson@arm.com ruby_port = system.ruby._cpu_ports[i] 26410066Sandreas.hansson@arm.com 26510066Sandreas.hansson@arm.com # Create the interrupt controller and connect its ports to Ruby 26610066Sandreas.hansson@arm.com # Note that the interrupt controller is always present but only 26710066Sandreas.hansson@arm.com # in x86 does it have message ports that need to be connected 26810066Sandreas.hansson@arm.com system.cpu[i].createInterruptController() 26910066Sandreas.hansson@arm.com 27010066Sandreas.hansson@arm.com # Connect the cpu's cache ports to Ruby 27110066Sandreas.hansson@arm.com system.cpu[i].icache_port = ruby_port.slave 27210066Sandreas.hansson@arm.com system.cpu[i].dcache_port = ruby_port.slave 27310405Sandreas.hansson@arm.com if buildEnv['TARGET_ISA'] == 'x86': 27410066Sandreas.hansson@arm.com system.cpu[i].interrupts[0].pio = ruby_port.master 27510066Sandreas.hansson@arm.com system.cpu[i].interrupts[0].int_master = ruby_port.slave 27610066Sandreas.hansson@arm.com system.cpu[i].interrupts[0].int_slave = ruby_port.master 27710066Sandreas.hansson@arm.com system.cpu[i].itb.walker.port = ruby_port.slave 27810066Sandreas.hansson@arm.com system.cpu[i].dtb.walker.port = ruby_port.slave 27910066Sandreas.hansson@arm.comelse: 28010066Sandreas.hansson@arm.com MemClass = Simulation.setMemClass(options) 28110066Sandreas.hansson@arm.com system.membus = SystemXBar() 28210066Sandreas.hansson@arm.com system.system_port = system.membus.slave 28310066Sandreas.hansson@arm.com CacheConfig.config_cache(options, system) 28410066Sandreas.hansson@arm.com MemConfig.config_mem(options, system) 28510066Sandreas.hansson@arm.com 28610066Sandreas.hansson@arm.comroot = Root(full_system = False, system = system) 28710066Sandreas.hansson@arm.comSimulation.run(options, root, system, FutureClass) 28810066Sandreas.hansson@arm.com