se.py revision 11251:a15c86af004a 
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
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11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
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38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47import os
48
49import m5
50from m5.defines import buildEnv
51from m5.objects import *
52from m5.util import addToPath, fatal
53
54addToPath('../common')
55addToPath('../ruby')
56
57import Options
58import Ruby
59import Simulation
60import CacheConfig
61import CpuConfig
62import MemConfig
63from Caches import *
64from cpu2000 import *
65
66# Check if KVM support has been enabled, we might need to do VM
67# configuration if that's the case.
68have_kvm_support = 'BaseKvmCPU' in globals()
69def is_kvm_cpu(cpu_class):
70    return have_kvm_support and cpu_class != None and \
71        issubclass(cpu_class, BaseKvmCPU)
72
73def get_processes(options):
74    """Interprets provided options and returns a list of processes"""
75
76    multiprocesses = []
77    inputs = []
78    outputs = []
79    errouts = []
80    pargs = []
81
82    workloads = options.cmd.split(';')
83    if options.input != "":
84        inputs = options.input.split(';')
85    if options.output != "":
86        outputs = options.output.split(';')
87    if options.errout != "":
88        errouts = options.errout.split(';')
89    if options.options != "":
90        pargs = options.options.split(';')
91
92    idx = 0
93    for wrkld in workloads:
94        process = LiveProcess()
95        process.executable = wrkld
96        process.cwd = os.getcwd()
97
98        if options.env:
99            with open(options.env, 'r') as f:
100                process.env = [line.rstrip() for line in f]
101
102        if len(pargs) > idx:
103            process.cmd = [wrkld] + pargs[idx].split()
104        else:
105            process.cmd = [wrkld]
106
107        if len(inputs) > idx:
108            process.input = inputs[idx]
109        if len(outputs) > idx:
110            process.output = outputs[idx]
111        if len(errouts) > idx:
112            process.errout = errouts[idx]
113
114        multiprocesses.append(process)
115        idx += 1
116
117    if options.smt:
118        assert(options.cpu_type == "detailed")
119        return multiprocesses, idx
120    else:
121        return multiprocesses, 1
122
123
124parser = optparse.OptionParser()
125Options.addCommonOptions(parser)
126Options.addSEOptions(parser)
127
128if '--ruby' in sys.argv:
129    Ruby.define_options(parser)
130
131(options, args) = parser.parse_args()
132
133if args:
134    print "Error: script doesn't take any positional arguments"
135    sys.exit(1)
136
137multiprocesses = []
138numThreads = 1
139
140if options.bench:
141    apps = options.bench.split("-")
142    if len(apps) != options.num_cpus:
143        print "number of benchmarks not equal to set num_cpus!"
144        sys.exit(1)
145
146    for app in apps:
147        try:
148            if buildEnv['TARGET_ISA'] == 'alpha':
149                exec("workload = %s('alpha', 'tru64', '%s')" % (
150                        app, options.spec_input))
151            elif buildEnv['TARGET_ISA'] == 'arm':
152                exec("workload = %s('arm_%s', 'linux', '%s')" % (
153                        app, options.arm_iset, options.spec_input))
154            else:
155                exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
156                        app, options.spec_input))
157            multiprocesses.append(workload.makeLiveProcess())
158        except:
159            print >>sys.stderr, "Unable to find workload for %s: %s" % (
160                    buildEnv['TARGET_ISA'], app)
161            sys.exit(1)
162elif options.cmd:
163    multiprocesses, numThreads = get_processes(options)
164else:
165    print >> sys.stderr, "No workload specified. Exiting!\n"
166    sys.exit(1)
167
168
169(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
170CPUClass.numThreads = numThreads
171
172# Check -- do not allow SMT with multiple CPUs
173if options.smt and options.num_cpus > 1:
174    fatal("You cannot use SMT with multiple CPUs!")
175
176np = options.num_cpus
177system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
178                mem_mode = test_mem_mode,
179                mem_ranges = [AddrRange(options.mem_size)],
180                cache_line_size = options.cacheline_size)
181
182if numThreads > 1:
183    system.multi_thread = True
184
185# Create a top-level voltage domain
186system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
187
188# Create a source clock for the system and set the clock period
189system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
190                                   voltage_domain = system.voltage_domain)
191
192# Create a CPU voltage domain
193system.cpu_voltage_domain = VoltageDomain()
194
195# Create a separate clock domain for the CPUs
196system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
197                                       voltage_domain =
198                                       system.cpu_voltage_domain)
199
200# If elastic tracing is enabled, then configure the cpu and attach the elastic
201# trace probe
202if options.elastic_trace_en:
203    CpuConfig.config_etrace(CPUClass, system.cpu, options)
204
205# All cpus belong to a common cpu_clk_domain, therefore running at a common
206# frequency.
207for cpu in system.cpu:
208    cpu.clk_domain = system.cpu_clk_domain
209
210if is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass):
211    if buildEnv['TARGET_ISA'] == 'x86':
212        system.vm = KvmVM()
213        for process in multiprocesses:
214            process.useArchPT = True
215            process.kvmInSE = True
216    else:
217        fatal("KvmCPU can only be used in SE mode with x86")
218
219# Sanity check
220if options.fastmem:
221    if CPUClass != AtomicSimpleCPU:
222        fatal("Fastmem can only be used with atomic CPU!")
223    if (options.caches or options.l2cache):
224        fatal("You cannot use fastmem in combination with caches!")
225
226if options.simpoint_profile:
227    if not options.fastmem:
228        # Atomic CPU checked with fastmem option already
229        fatal("SimPoint generation should be done with atomic cpu and fastmem")
230    if np > 1:
231        fatal("SimPoint generation not supported with more than one CPUs")
232
233for i in xrange(np):
234    if options.smt:
235        system.cpu[i].workload = multiprocesses
236    elif len(multiprocesses) == 1:
237        system.cpu[i].workload = multiprocesses[0]
238    else:
239        system.cpu[i].workload = multiprocesses[i]
240
241    if options.fastmem:
242        system.cpu[i].fastmem = True
243
244    if options.simpoint_profile:
245        system.cpu[i].addSimPointProbe(options.simpoint_interval)
246
247    if options.checker:
248        system.cpu[i].addCheckerCpu()
249
250    system.cpu[i].createThreads()
251
252if options.ruby:
253    if options.cpu_type == "atomic" or options.cpu_type == "AtomicSimpleCPU":
254        print >> sys.stderr, "Ruby does not work with atomic cpu!!"
255        sys.exit(1)
256
257    Ruby.create_system(options, False, system)
258    assert(options.num_cpus == len(system.ruby._cpu_ports))
259
260    system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
261                                        voltage_domain = system.voltage_domain)
262    for i in xrange(np):
263        ruby_port = system.ruby._cpu_ports[i]
264
265        # Create the interrupt controller and connect its ports to Ruby
266        # Note that the interrupt controller is always present but only
267        # in x86 does it have message ports that need to be connected
268        system.cpu[i].createInterruptController()
269
270        # Connect the cpu's cache ports to Ruby
271        system.cpu[i].icache_port = ruby_port.slave
272        system.cpu[i].dcache_port = ruby_port.slave
273        if buildEnv['TARGET_ISA'] == 'x86':
274            system.cpu[i].interrupts[0].pio = ruby_port.master
275            system.cpu[i].interrupts[0].int_master = ruby_port.slave
276            system.cpu[i].interrupts[0].int_slave = ruby_port.master
277            system.cpu[i].itb.walker.port = ruby_port.slave
278            system.cpu[i].dtb.walker.port = ruby_port.slave
279else:
280    MemClass = Simulation.setMemClass(options)
281    system.membus = SystemXBar()
282    system.system_port = system.membus.slave
283    CacheConfig.config_cache(options, system)
284    MemConfig.config_mem(options, system)
285
286root = Root(full_system = False, system = system)
287Simulation.run(options, root, system, FutureClass)
288