se.py revision 10803:a91eb7b4a442 
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
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9# terms below provided that you ensure that this notice is replicated
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11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# All rights reserved.
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38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47import os
48
49import m5
50from m5.defines import buildEnv
51from m5.objects import *
52from m5.util import addToPath, fatal
53
54addToPath('../common')
55addToPath('../ruby')
56
57import Options
58import Ruby
59import Simulation
60import CacheConfig
61import MemConfig
62from Caches import *
63from cpu2000 import *
64
65# Check if KVM support has been enabled, we might need to do VM
66# configuration if that's the case.
67have_kvm_support = 'BaseKvmCPU' in globals()
68def is_kvm_cpu(cpu_class):
69    return have_kvm_support and cpu_class != None and \
70        issubclass(cpu_class, BaseKvmCPU)
71
72def get_processes(options):
73    """Interprets provided options and returns a list of processes"""
74
75    multiprocesses = []
76    inputs = []
77    outputs = []
78    errouts = []
79    pargs = []
80
81    workloads = options.cmd.split(';')
82    if options.input != "":
83        inputs = options.input.split(';')
84    if options.output != "":
85        outputs = options.output.split(';')
86    if options.errout != "":
87        errouts = options.errout.split(';')
88    if options.options != "":
89        pargs = options.options.split(';')
90
91    idx = 0
92    for wrkld in workloads:
93        process = LiveProcess()
94        process.executable = wrkld
95        process.cwd = os.getcwd()
96
97        if options.env:
98            with open(options.env, 'r') as f:
99                process.env = [line.rstrip() for line in f]
100
101        if len(pargs) > idx:
102            process.cmd = [wrkld] + pargs[idx].split()
103        else:
104            process.cmd = [wrkld]
105
106        if len(inputs) > idx:
107            process.input = inputs[idx]
108        if len(outputs) > idx:
109            process.output = outputs[idx]
110        if len(errouts) > idx:
111            process.errout = errouts[idx]
112
113        multiprocesses.append(process)
114        idx += 1
115
116    if options.smt:
117        assert(options.cpu_type == "detailed")
118        return multiprocesses, idx
119    else:
120        return multiprocesses, 1
121
122
123parser = optparse.OptionParser()
124Options.addCommonOptions(parser)
125Options.addSEOptions(parser)
126
127if '--ruby' in sys.argv:
128    Ruby.define_options(parser)
129
130(options, args) = parser.parse_args()
131
132if args:
133    print "Error: script doesn't take any positional arguments"
134    sys.exit(1)
135
136multiprocesses = []
137numThreads = 1
138
139if options.bench:
140    apps = options.bench.split("-")
141    if len(apps) != options.num_cpus:
142        print "number of benchmarks not equal to set num_cpus!"
143        sys.exit(1)
144
145    for app in apps:
146        try:
147            if buildEnv['TARGET_ISA'] == 'alpha':
148                exec("workload = %s('alpha', 'tru64', '%s')" % (
149                        app, options.spec_input))
150            elif buildEnv['TARGET_ISA'] == 'arm':
151                exec("workload = %s('arm_%s', 'linux', '%s')" % (
152                        app, options.arm_iset, options.spec_input))
153            else:
154                exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
155                        app, options.spec_input))
156            multiprocesses.append(workload.makeLiveProcess())
157        except:
158            print >>sys.stderr, "Unable to find workload for %s: %s" % (
159                    buildEnv['TARGET_ISA'], app)
160            sys.exit(1)
161elif options.cmd:
162    multiprocesses, numThreads = get_processes(options)
163else:
164    print >> sys.stderr, "No workload specified. Exiting!\n"
165    sys.exit(1)
166
167
168(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
169CPUClass.numThreads = numThreads
170
171# Check -- do not allow SMT with multiple CPUs
172if options.smt and options.num_cpus > 1:
173    fatal("You cannot use SMT with multiple CPUs!")
174
175np = options.num_cpus
176system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
177                mem_mode = test_mem_mode,
178                mem_ranges = [AddrRange(options.mem_size)],
179                cache_line_size = options.cacheline_size)
180
181# Create a top-level voltage domain
182system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
183
184# Create a source clock for the system and set the clock period
185system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
186                                   voltage_domain = system.voltage_domain)
187
188# Create a CPU voltage domain
189system.cpu_voltage_domain = VoltageDomain()
190
191# Create a separate clock domain for the CPUs
192system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
193                                       voltage_domain =
194                                       system.cpu_voltage_domain)
195
196# All cpus belong to a common cpu_clk_domain, therefore running at a common
197# frequency.
198for cpu in system.cpu:
199    cpu.clk_domain = system.cpu_clk_domain
200
201if is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass):
202    if buildEnv['TARGET_ISA'] == 'x86':
203        system.vm = KvmVM()
204        for process in multiprocesses:
205            process.useArchPT = True
206            process.kvmInSE = True
207    else:
208        fatal("KvmCPU can only be used in SE mode with x86")
209
210# Sanity check
211if options.fastmem:
212    if CPUClass != AtomicSimpleCPU:
213        fatal("Fastmem can only be used with atomic CPU!")
214    if (options.caches or options.l2cache):
215        fatal("You cannot use fastmem in combination with caches!")
216
217if options.simpoint_profile:
218    if not options.fastmem:
219        # Atomic CPU checked with fastmem option already
220        fatal("SimPoint generation should be done with atomic cpu and fastmem")
221    if np > 1:
222        fatal("SimPoint generation not supported with more than one CPUs")
223
224for i in xrange(np):
225    if options.smt:
226        system.cpu[i].workload = multiprocesses
227    elif len(multiprocesses) == 1:
228        system.cpu[i].workload = multiprocesses[0]
229    else:
230        system.cpu[i].workload = multiprocesses[i]
231
232    if options.fastmem:
233        system.cpu[i].fastmem = True
234
235    if options.simpoint_profile:
236        system.cpu[i].addSimPointProbe(options.simpoint_interval)
237
238    if options.checker:
239        system.cpu[i].addCheckerCpu()
240
241    system.cpu[i].createThreads()
242
243if options.ruby:
244    if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
245        print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
246        sys.exit(1)
247
248    Ruby.create_system(options, False, system)
249    assert(options.num_cpus == len(system.ruby._cpu_ports))
250
251    system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
252                                        voltage_domain = system.voltage_domain)
253    for i in xrange(np):
254        ruby_port = system.ruby._cpu_ports[i]
255
256        # Create the interrupt controller and connect its ports to Ruby
257        # Note that the interrupt controller is always present but only
258        # in x86 does it have message ports that need to be connected
259        system.cpu[i].createInterruptController()
260
261        # Connect the cpu's cache ports to Ruby
262        system.cpu[i].icache_port = ruby_port.slave
263        system.cpu[i].dcache_port = ruby_port.slave
264        if buildEnv['TARGET_ISA'] == 'x86':
265            system.cpu[i].interrupts.pio = ruby_port.master
266            system.cpu[i].interrupts.int_master = ruby_port.slave
267            system.cpu[i].interrupts.int_slave = ruby_port.master
268            system.cpu[i].itb.walker.port = ruby_port.slave
269            system.cpu[i].dtb.walker.port = ruby_port.slave
270else:
271    MemClass = Simulation.setMemClass(options)
272    system.membus = SystemXBar()
273    system.system_port = system.membus.slave
274    CacheConfig.config_cache(options, system)
275    MemConfig.config_mem(options, system)
276
277root = Root(full_system = False, system = system)
278Simulation.run(options, root, system, FutureClass)
279