se.py revision 10547:b61dc895269a
12810SN/A# Copyright (c) 2012-2013 ARM Limited 213932Snikos.nikoleris@arm.com# All rights reserved. 38856Sandreas.hansson@arm.com# 48856Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58856Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68856Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78856Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88856Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98856Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108856Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118856Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128856Sandreas.hansson@arm.com# 138856Sandreas.hansson@arm.com# Copyright (c) 2006-2008 The Regents of The University of Michigan 142810SN/A# All rights reserved. 152810SN/A# 162810SN/A# Redistribution and use in source and binary forms, with or without 172810SN/A# modification, are permitted provided that the following conditions are 182810SN/A# met: redistributions of source code must retain the above copyright 192810SN/A# notice, this list of conditions and the following disclaimer; 202810SN/A# redistributions in binary form must reproduce the above copyright 212810SN/A# notice, this list of conditions and the following disclaimer in the 222810SN/A# documentation and/or other materials provided with the distribution; 232810SN/A# neither the name of the copyright holders nor the names of its 242810SN/A# contributors may be used to endorse or promote products derived from 252810SN/A# this software without specific prior written permission. 262810SN/A# 272810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312810SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322810SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332810SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342810SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362810SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382810SN/A# 392810SN/A# Authors: Steve Reinhardt 402810SN/A 4112724Snikos.nikoleris@arm.com# Simple test script 422810SN/A# 432810SN/A# "m5 test.py" 442810SN/A 452810SN/Aimport optparse 462810SN/Aimport sys 472810SN/Aimport os 482810SN/A 4911486Snikos.nikoleris@arm.comimport m5 5011486Snikos.nikoleris@arm.comfrom m5.defines import buildEnv 5112724Snikos.nikoleris@arm.comfrom m5.objects import * 5212724Snikos.nikoleris@arm.comfrom m5.util import addToPath, fatal 538232Snate@binkert.org 5412724Snikos.nikoleris@arm.comaddToPath('../common') 5513222Sodanrc@yahoo.com.braddToPath('../ruby') 5612724Snikos.nikoleris@arm.com 5713945Sodanrc@yahoo.com.brimport Options 5811486Snikos.nikoleris@arm.comimport Ruby 5912724Snikos.nikoleris@arm.comimport Simulation 6012724Snikos.nikoleris@arm.comimport CacheConfig 6112724Snikos.nikoleris@arm.comimport MemConfig 6213352Snikos.nikoleris@arm.comfrom Caches import * 6312724Snikos.nikoleris@arm.comfrom cpu2000 import * 6412724Snikos.nikoleris@arm.com 6512724Snikos.nikoleris@arm.comdef get_processes(options): 6612724Snikos.nikoleris@arm.com """Interprets provided options and returns a list of processes""" 672810SN/A 682810SN/A multiprocesses = [] 692810SN/A inputs = [] 708856Sandreas.hansson@arm.com outputs = [] 718856Sandreas.hansson@arm.com errouts = [] 728856Sandreas.hansson@arm.com pargs = [] 7313564Snikos.nikoleris@arm.com 7413564Snikos.nikoleris@arm.com workloads = options.cmd.split(';') 7512084Sspwilson2@wisc.edu if options.input != "": 7612084Sspwilson2@wisc.edu inputs = options.input.split(';') 778856Sandreas.hansson@arm.com if options.output != "": 788856Sandreas.hansson@arm.com outputs = options.output.split(';') 794475SN/A if options.errout != "": 8011053Sandreas.hansson@arm.com errouts = options.errout.split(';') 8113892Sgabeblack@google.com if options.options != "": 8212724Snikos.nikoleris@arm.com pargs = options.options.split(';') 8312724Snikos.nikoleris@arm.com 8411377Sandreas.hansson@arm.com idx = 0 8511377Sandreas.hansson@arm.com for wrkld in workloads: 8612724Snikos.nikoleris@arm.com process = LiveProcess() 8713945Sodanrc@yahoo.com.br process.executable = wrkld 8812724Snikos.nikoleris@arm.com process.cwd = os.getcwd() 8913352Snikos.nikoleris@arm.com 9012724Snikos.nikoleris@arm.com if len(pargs) > idx: 9112724Snikos.nikoleris@arm.com process.cmd = [wrkld] + pargs[idx].split() 9212724Snikos.nikoleris@arm.com else: 9312724Snikos.nikoleris@arm.com process.cmd = [wrkld] 9412724Snikos.nikoleris@arm.com 9511053Sandreas.hansson@arm.com if len(inputs) > idx: 9611722Ssophiane.senni@gmail.com process.input = inputs[idx] 9711722Ssophiane.senni@gmail.com if len(outputs) > idx: 9811722Ssophiane.senni@gmail.com process.output = outputs[idx] 9911722Ssophiane.senni@gmail.com if len(errouts) > idx: 1009263Smrinmoy.ghosh@arm.com process.errout = errouts[idx] 10113418Sodanrc@yahoo.com.br 1025034SN/A multiprocesses.append(process) 10311331Sandreas.hansson@arm.com idx += 1 10412724Snikos.nikoleris@arm.com 10510884Sandreas.hansson@arm.com if options.smt: 1064626SN/A assert(options.cpu_type == "detailed" or options.cpu_type == "inorder") 10710360Sandreas.hansson@arm.com return multiprocesses, idx 10811484Snikos.nikoleris@arm.com else: 1095034SN/A return multiprocesses, 1 1108883SAli.Saidi@ARM.com 1118833Sdam.sunwoo@arm.com 1124458SN/Aparser = optparse.OptionParser() 11311377Sandreas.hansson@arm.comOptions.addCommonOptions(parser) 11411377Sandreas.hansson@arm.comOptions.addSEOptions(parser) 11511377Sandreas.hansson@arm.com 11611377Sandreas.hansson@arm.comif '--ruby' in sys.argv: 11711377Sandreas.hansson@arm.com Ruby.define_options(parser) 11811377Sandreas.hansson@arm.com 11911331Sandreas.hansson@arm.com(options, args) = parser.parse_args() 12011331Sandreas.hansson@arm.com 12112724Snikos.nikoleris@arm.comif args: 12212843Srmk35@cl.cam.ac.uk print "Error: script doesn't take any positional arguments" 12312724Snikos.nikoleris@arm.com sys.exit(1) 12413419Sodanrc@yahoo.com.br 12512724Snikos.nikoleris@arm.commultiprocesses = [] 12612724Snikos.nikoleris@arm.comnumThreads = 1 12712724Snikos.nikoleris@arm.com 12812724Snikos.nikoleris@arm.comif options.bench: 12912724Snikos.nikoleris@arm.com apps = options.bench.split("-") 13012724Snikos.nikoleris@arm.com if len(apps) != options.num_cpus: 13112724Snikos.nikoleris@arm.com print "number of benchmarks not equal to set num_cpus!" 1322810SN/A sys.exit(1) 1332810SN/A 1343013SN/A for app in apps: 1358856Sandreas.hansson@arm.com try: 1362810SN/A if buildEnv['TARGET_ISA'] == 'alpha': 1373013SN/A exec("workload = %s('alpha', 'tru64', '%s')" % ( 13810714Sandreas.hansson@arm.com app, options.spec_input)) 1392810SN/A elif buildEnv['TARGET_ISA'] == 'arm': 1409614Srene.dejong@arm.com exec("workload = %s('arm_%s', 'linux', '%s')" % ( 1419614Srene.dejong@arm.com app, options.arm_iset, options.spec_input)) 1429614Srene.dejong@arm.com else: 14310345SCurtis.Dunham@arm.com exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % ( 14410714Sandreas.hansson@arm.com app, options.spec_input)) 14510345SCurtis.Dunham@arm.com multiprocesses.append(workload.makeLiveProcess()) 1469614Srene.dejong@arm.com except: 1472810SN/A print >>sys.stderr, "Unable to find workload for %s: %s" % ( 1482810SN/A buildEnv['TARGET_ISA'], app) 1492810SN/A sys.exit(1) 1508856Sandreas.hansson@arm.comelif options.cmd: 1512810SN/A multiprocesses, numThreads = get_processes(options) 1523013SN/Aelse: 15310714Sandreas.hansson@arm.com print >> sys.stderr, "No workload specified. Exiting!\n" 1543013SN/A sys.exit(1) 1558856Sandreas.hansson@arm.com 15610714Sandreas.hansson@arm.com 1578922Swilliam.wang@arm.com(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 1582897SN/ACPUClass.numThreads = numThreads 1592810SN/A 1602810SN/A# Check -- do not allow SMT with multiple CPUs 16110344Sandreas.hansson@arm.comif options.smt and options.num_cpus > 1: 16210344Sandreas.hansson@arm.com fatal("You cannot use SMT with multiple CPUs!") 16310344Sandreas.hansson@arm.com 16410714Sandreas.hansson@arm.comnp = options.num_cpus 16510344Sandreas.hansson@arm.comsystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 16610344Sandreas.hansson@arm.com mem_mode = test_mem_mode, 16710344Sandreas.hansson@arm.com mem_ranges = [AddrRange(options.mem_size)], 16810713Sandreas.hansson@arm.com cache_line_size = options.cacheline_size) 16910344Sandreas.hansson@arm.com 1702844SN/A# Create a top-level voltage domain 17112730Sodanrc@yahoo.com.brsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 17212730Sodanrc@yahoo.com.br 17312730Sodanrc@yahoo.com.br# Create a source clock for the system and set the clock period 17412730Sodanrc@yahoo.com.brsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 17512730Sodanrc@yahoo.com.br voltage_domain = system.voltage_domain) 17612730Sodanrc@yahoo.com.br 17712730Sodanrc@yahoo.com.br# Create a CPU voltage domain 17812730Sodanrc@yahoo.com.brsystem.cpu_voltage_domain = VoltageDomain() 17912730Sodanrc@yahoo.com.br 18012730Sodanrc@yahoo.com.br# Create a separate clock domain for the CPUs 1812810SN/Asystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1822858SN/A voltage_domain = 1832858SN/A system.cpu_voltage_domain) 18412724Snikos.nikoleris@arm.com 1858922Swilliam.wang@arm.com# All cpus belong to a common cpu_clk_domain, therefore running at a common 18612724Snikos.nikoleris@arm.com# frequency. 18712724Snikos.nikoleris@arm.comfor cpu in system.cpu: 1882858SN/A cpu.clk_domain = system.cpu_clk_domain 1892858SN/A 19013784Sgabeblack@google.com# Sanity check 19113784Sgabeblack@google.comif options.fastmem: 1928922Swilliam.wang@arm.com if CPUClass != AtomicSimpleCPU: 1938922Swilliam.wang@arm.com fatal("Fastmem can only be used with atomic CPU!") 19412724Snikos.nikoleris@arm.com if (options.caches or options.l2cache): 19513784Sgabeblack@google.com fatal("You cannot use fastmem in combination with caches!") 19613784Sgabeblack@google.com 1978922Swilliam.wang@arm.comif options.simpoint_profile: 19813892Sgabeblack@google.com if not options.fastmem: 1998922Swilliam.wang@arm.com # Atomic CPU checked with fastmem option already 2008922Swilliam.wang@arm.com fatal("SimPoint generation should be done with atomic cpu and fastmem") 2014628SN/A if np > 1: 20210821Sandreas.hansson@arm.com fatal("SimPoint generation not supported with more than one CPUs") 20310821Sandreas.hansson@arm.com 20410821Sandreas.hansson@arm.comfor i in xrange(np): 20510821Sandreas.hansson@arm.com if options.smt: 20610821Sandreas.hansson@arm.com system.cpu[i].workload = multiprocesses 20710821Sandreas.hansson@arm.com elif len(multiprocesses) == 1: 20810821Sandreas.hansson@arm.com system.cpu[i].workload = multiprocesses[0] 20910821Sandreas.hansson@arm.com else: 21010821Sandreas.hansson@arm.com system.cpu[i].workload = multiprocesses[i] 21110821Sandreas.hansson@arm.com 21210821Sandreas.hansson@arm.com if options.fastmem: 2132858SN/A system.cpu[i].fastmem = True 21412724Snikos.nikoleris@arm.com 21512724Snikos.nikoleris@arm.com if options.simpoint_profile: 21612724Snikos.nikoleris@arm.com system.cpu[i].addSimPointProbe(options.simpoint_interval) 21713745Sodanrc@yahoo.com.br 21813745Sodanrc@yahoo.com.br if options.checker: 21913745Sodanrc@yahoo.com.br system.cpu[i].addCheckerCpu() 22013745Sodanrc@yahoo.com.br 22112724Snikos.nikoleris@arm.com system.cpu[i].createThreads() 22212724Snikos.nikoleris@arm.com 22312724Snikos.nikoleris@arm.comif options.ruby: 22412724Snikos.nikoleris@arm.com if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 22512724Snikos.nikoleris@arm.com print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 22613418Sodanrc@yahoo.com.br sys.exit(1) 22713418Sodanrc@yahoo.com.br 22813564Snikos.nikoleris@arm.com Ruby.create_system(options, False, system) 22912724Snikos.nikoleris@arm.com assert(options.num_cpus == len(system.ruby._cpu_ports)) 23012724Snikos.nikoleris@arm.com 23112724Snikos.nikoleris@arm.com system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 23212724Snikos.nikoleris@arm.com voltage_domain = system.voltage_domain) 23312724Snikos.nikoleris@arm.com for i in xrange(np): 23412724Snikos.nikoleris@arm.com ruby_port = system.ruby._cpu_ports[i] 23512724Snikos.nikoleris@arm.com 23612724Snikos.nikoleris@arm.com # Create the interrupt controller and connect its ports to Ruby 23712724Snikos.nikoleris@arm.com # Note that the interrupt controller is always present but only 23812724Snikos.nikoleris@arm.com # in x86 does it have message ports that need to be connected 23912724Snikos.nikoleris@arm.com system.cpu[i].createInterruptController() 24012724Snikos.nikoleris@arm.com 24112724Snikos.nikoleris@arm.com # Connect the cpu's cache ports to Ruby 24212724Snikos.nikoleris@arm.com system.cpu[i].icache_port = ruby_port.slave 24312724Snikos.nikoleris@arm.com system.cpu[i].dcache_port = ruby_port.slave 24412724Snikos.nikoleris@arm.com if buildEnv['TARGET_ISA'] == 'x86': 24513352Snikos.nikoleris@arm.com system.cpu[i].interrupts.pio = ruby_port.master 24613352Snikos.nikoleris@arm.com system.cpu[i].interrupts.int_master = ruby_port.slave 24713352Snikos.nikoleris@arm.com system.cpu[i].interrupts.int_slave = ruby_port.master 24813352Snikos.nikoleris@arm.com system.cpu[i].itb.walker.port = ruby_port.slave 24913352Snikos.nikoleris@arm.com system.cpu[i].dtb.walker.port = ruby_port.slave 25013352Snikos.nikoleris@arm.comelse: 25112724Snikos.nikoleris@arm.com MemClass = Simulation.setMemClass(options) 25212724Snikos.nikoleris@arm.com system.membus = CoherentXBar() 25312724Snikos.nikoleris@arm.com system.system_port = system.membus.slave 25412724Snikos.nikoleris@arm.com CacheConfig.config_cache(options, system) 25512724Snikos.nikoleris@arm.com MemConfig.config_mem(options, system) 25612724Snikos.nikoleris@arm.com 25712724Snikos.nikoleris@arm.comroot = Root(full_system = False, system = system) 25812724Snikos.nikoleris@arm.comSimulation.run(options, root, system, FutureClass) 25912724Snikos.nikoleris@arm.com