se.py revision 9217
18706Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited
28706Sandreas.hansson@arm.com# All rights reserved.
38706Sandreas.hansson@arm.com#
48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall
58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual
68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating
78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software
88706Sandreas.hansson@arm.com# licensed hereunder.  You may use the software subject to the license
98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated
108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software,
118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form.
128706Sandreas.hansson@arm.com#
135369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan
143005Sstever@eecs.umich.edu# All rights reserved.
153005Sstever@eecs.umich.edu#
163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are
183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright
193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution;
233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its
243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from
253005Sstever@eecs.umich.edu# this software without specific prior written permission.
263005Sstever@eecs.umich.edu#
273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
383005Sstever@eecs.umich.edu#
393005Sstever@eecs.umich.edu# Authors: Steve Reinhardt
403005Sstever@eecs.umich.edu
412710SN/A# Simple test script
422710SN/A#
433005Sstever@eecs.umich.edu# "m5 test.py"
442889SN/A
456654Snate@binkert.orgimport optparse
466654Snate@binkert.orgimport sys
476654Snate@binkert.org
482667SN/Aimport m5
496654Snate@binkert.orgfrom m5.defines import buildEnv
506654Snate@binkert.orgfrom m5.objects import *
516654Snate@binkert.orgfrom m5.util import addToPath, fatal
525457Ssaidi@eecs.umich.edu
536654Snate@binkert.orgaddToPath('../common')
548169SLisa.Hsu@amd.comaddToPath('../ruby')
559100SBrad.Beckmann@amd.comaddToPath('../topologies')
568169SLisa.Hsu@amd.com
578920Snilay@cs.wisc.eduimport Options
588169SLisa.Hsu@amd.comimport Ruby
593395Shsul@eecs.umich.eduimport Simulation
606981SLisa.Hsu@amd.comimport CacheConfig
613448Shsul@eecs.umich.edufrom Caches import *
625369Ssaidi@eecs.umich.edufrom cpu2000 import *
633394Shsul@eecs.umich.edu
649197Snilay@cs.wisc.edudef get_processes(options):
659197Snilay@cs.wisc.edu    """Interprets provided options and returns a list of processes"""
669197Snilay@cs.wisc.edu
679197Snilay@cs.wisc.edu    multiprocesses = []
689197Snilay@cs.wisc.edu    inputs = []
699197Snilay@cs.wisc.edu    outputs = []
709197Snilay@cs.wisc.edu    errouts = []
719197Snilay@cs.wisc.edu    pargs = []
729197Snilay@cs.wisc.edu
739197Snilay@cs.wisc.edu    workloads = options.cmd.split(';')
749197Snilay@cs.wisc.edu    if options.input != "":
759197Snilay@cs.wisc.edu        inputs = options.input.split(';')
769197Snilay@cs.wisc.edu    if options.output != "":
779197Snilay@cs.wisc.edu        outputs = options.output.split(';')
789197Snilay@cs.wisc.edu    if options.errout != "":
799197Snilay@cs.wisc.edu        errouts = options.errout.split(';')
809197Snilay@cs.wisc.edu    if options.options != "":
819197Snilay@cs.wisc.edu        pargs = options.options.split(';')
829197Snilay@cs.wisc.edu
839197Snilay@cs.wisc.edu    idx = 0
849197Snilay@cs.wisc.edu    for wrkld in workloads:
859197Snilay@cs.wisc.edu        process = LiveProcess()
869197Snilay@cs.wisc.edu        process.executable = wrkld
879197Snilay@cs.wisc.edu
889197Snilay@cs.wisc.edu        if len(pargs) > idx:
899217Snilay@cs.wisc.edu            process.cmd = [wrkld] + pargs[idx].split()
909197Snilay@cs.wisc.edu        else:
919197Snilay@cs.wisc.edu            process.cmd = [wrkld]
929197Snilay@cs.wisc.edu
939197Snilay@cs.wisc.edu        if len(inputs) > idx:
949197Snilay@cs.wisc.edu            process.input = inputs[idx]
959197Snilay@cs.wisc.edu        if len(outputs) > idx:
969197Snilay@cs.wisc.edu            process.output = outputs[idx]
979197Snilay@cs.wisc.edu        if len(errouts) > idx:
989197Snilay@cs.wisc.edu            process.errout = errouts[idx]
999197Snilay@cs.wisc.edu
1009197Snilay@cs.wisc.edu        multiprocesses.append(process)
1019197Snilay@cs.wisc.edu        idx += 1
1029197Snilay@cs.wisc.edu
1039197Snilay@cs.wisc.edu    if options.smt:
1049197Snilay@cs.wisc.edu        assert(options.cpu_type == "detailed" or options.cpu_type == "inorder")
1059197Snilay@cs.wisc.edu        return multiprocesses, idx
1069197Snilay@cs.wisc.edu    else:
1079197Snilay@cs.wisc.edu        return multiprocesses, 1
1089197Snilay@cs.wisc.edu
1099197Snilay@cs.wisc.edu
1102957SN/Aparser = optparse.OptionParser()
1118920Snilay@cs.wisc.eduOptions.addCommonOptions(parser)
1128920Snilay@cs.wisc.eduOptions.addSEOptions(parser)
1132957SN/A
1148862Snilay@cs.wisc.eduif '--ruby' in sys.argv:
1158862Snilay@cs.wisc.edu    Ruby.define_options(parser)
1168467Snilay@cs.wisc.edu
1172957SN/A(options, args) = parser.parse_args()
1182957SN/A
1192957SN/Aif args:
1202957SN/A    print "Error: script doesn't take any positional arguments"
1212957SN/A    sys.exit(1)
1222957SN/A
1238167SLisa.Hsu@amd.commultiprocesses = []
1249197Snilay@cs.wisc.edunumThreads = 1
1258167SLisa.Hsu@amd.com
1265369Ssaidi@eecs.umich.eduif options.bench:
1278167SLisa.Hsu@amd.com    apps = options.bench.split("-")
1288167SLisa.Hsu@amd.com    if len(apps) != options.num_cpus:
1298167SLisa.Hsu@amd.com        print "number of benchmarks not equal to set num_cpus!"
1308167SLisa.Hsu@amd.com        sys.exit(1)
1318167SLisa.Hsu@amd.com
1328167SLisa.Hsu@amd.com    for app in apps:
1338167SLisa.Hsu@amd.com        try:
1348168SLisa.Hsu@amd.com            if buildEnv['TARGET_ISA'] == 'alpha':
1358168SLisa.Hsu@amd.com                exec("workload = %s('alpha', 'tru64', 'ref')" % app)
1368168SLisa.Hsu@amd.com            else:
1378168SLisa.Hsu@amd.com                exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
1388167SLisa.Hsu@amd.com            multiprocesses.append(workload.makeLiveProcess())
1398167SLisa.Hsu@amd.com        except:
1408168SLisa.Hsu@amd.com            print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
1415369Ssaidi@eecs.umich.edu            sys.exit(1)
1428920Snilay@cs.wisc.eduelif options.cmd:
1439197Snilay@cs.wisc.edu    multiprocesses, numThreads = get_processes(options)
1448920Snilay@cs.wisc.eduelse:
1458920Snilay@cs.wisc.edu    print >> sys.stderr, "No workload specified. Exiting!\n"
1468920Snilay@cs.wisc.edu    sys.exit(1)
1475369Ssaidi@eecs.umich.edu
1485369Ssaidi@eecs.umich.edu
1498718Snilay@cs.wisc.edu(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
1509129Sandreas.hansson@arm.comCPUClass.clock = options.clock
1519197Snilay@cs.wisc.eduCPUClass.numThreads = numThreads
1529197Snilay@cs.wisc.edu
1539197Snilay@cs.wisc.edu# Check -- do not allow SMT with multiple CPUs
1549197Snilay@cs.wisc.eduif options.smt and options.num_cpus > 1:
1559197Snilay@cs.wisc.edu    fatal("You cannot use SMT with multiple CPUs!")
1563005Sstever@eecs.umich.edu
1573395Shsul@eecs.umich.edunp = options.num_cpus
1583395Shsul@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
1598931Sandreas.hansson@arm.com                physmem = SimpleMemory(range=AddrRange("512MB")),
1609036Sandreas.hansson@arm.com                membus = CoherentBus(), mem_mode = test_mem_mode)
1613395Shsul@eecs.umich.edu
1628926Sandreas.hansson@arm.com# Sanity check
1638926Sandreas.hansson@arm.comif options.fastmem and (options.caches or options.l2cache):
1648926Sandreas.hansson@arm.com    fatal("You cannot use fastmem in combination with caches!")
1658926Sandreas.hansson@arm.com
1663395Shsul@eecs.umich.edufor i in xrange(np):
1679197Snilay@cs.wisc.edu    if options.smt:
1689197Snilay@cs.wisc.edu        system.cpu[i].workload = multiprocesses
1699197Snilay@cs.wisc.edu    elif len(multiprocesses) == 1:
1708957Sjayneel@cs.wisc.edu        system.cpu[i].workload = multiprocesses[0]
1718957Sjayneel@cs.wisc.edu    else:
1728957Sjayneel@cs.wisc.edu        system.cpu[i].workload = multiprocesses[i]
1733005Sstever@eecs.umich.edu
1744968Sacolyte@umich.edu    if options.fastmem:
1759006Sandreas.hansson@arm.com        system.cpu[i].fastmem = True
1764968Sacolyte@umich.edu
1778887Sgeoffrey.blake@arm.com    if options.checker:
1788887Sgeoffrey.blake@arm.com        system.cpu[i].addCheckerCpu()
1798887Sgeoffrey.blake@arm.com
1808887Sgeoffrey.blake@arm.comif options.ruby:
1818896Snilay@cs.wisc.edu    if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
1828896Snilay@cs.wisc.edu        print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
1838896Snilay@cs.wisc.edu        sys.exit(1)
1848896Snilay@cs.wisc.edu
1858887Sgeoffrey.blake@arm.com    options.use_map = True
1868887Sgeoffrey.blake@arm.com    Ruby.create_system(options, system)
1878887Sgeoffrey.blake@arm.com    assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
1888896Snilay@cs.wisc.edu
1898896Snilay@cs.wisc.edu    for i in xrange(np):
1908896Snilay@cs.wisc.edu        ruby_port = system.ruby._cpu_ruby_ports[i]
1918896Snilay@cs.wisc.edu
1928896Snilay@cs.wisc.edu        # Create the interrupt controller and connect its ports to Ruby
1938896Snilay@cs.wisc.edu        system.cpu[i].createInterruptController()
1948896Snilay@cs.wisc.edu        system.cpu[i].interrupts.pio = ruby_port.master
1958896Snilay@cs.wisc.edu        system.cpu[i].interrupts.int_master = ruby_port.slave
1968896Snilay@cs.wisc.edu        system.cpu[i].interrupts.int_slave = ruby_port.master
1978896Snilay@cs.wisc.edu
1988896Snilay@cs.wisc.edu        # Connect the cpu's cache ports to Ruby
1998896Snilay@cs.wisc.edu        system.cpu[i].icache_port = ruby_port.slave
2008896Snilay@cs.wisc.edu        system.cpu[i].dcache_port = ruby_port.slave
2018887Sgeoffrey.blake@arm.comelse:
2028887Sgeoffrey.blake@arm.com    system.system_port = system.membus.slave
2038887Sgeoffrey.blake@arm.com    system.physmem.port = system.membus.master
2048887Sgeoffrey.blake@arm.com    CacheConfig.config_cache(options, system)
2058887Sgeoffrey.blake@arm.com
2068801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system)
2073481Shsul@eecs.umich.eduSimulation.run(options, root, system, FutureClass)
208